-- IOTA Pearl Diver VHDL Port
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-- IOTA Pearl Diver VHDL Port
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--
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--
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-- Written 2018 by Thomas Pototschnig <microengineer18@gmail.com>
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-- 2018 by Thomas Pototschnig <microengineer18@gmail.com,
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--
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-- http://microengineer.eu
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-- This source code is currently licensed under
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-- discord: pmaxuw#8292
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-- Attribution-NonCommercial 4.0 International (CC BY-NC 4.0)
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--
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--
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-- Permission is hereby granted, free of charge, to any person obtaining
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-- http://www.microengineer.eu
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-- a copy of this software and associated documentation files (the
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--
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-- "Software"), to deal in the Software without restriction, including
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-- If you like my project please consider a donation to
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-- without limitation the rights to use, copy, modify, merge, publish,
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--
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-- distribute, sublicense, and/or sell copies of the Software, and to
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-- LLEYMHRKXWSPMGCMZFPKKTHSEMYJTNAZXSAYZGQUEXLXEEWPXUNWBFDWESOJVLHQHXOPQEYXGIRBYTLRWHMJAOSHUY
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-- permit persons to whom the Software is furnished to do so, subject to
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--
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-- the following conditions:
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-- As soon as donations reach 1000MIOTA, everything will become
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--
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-- GPL and open for any use - commercial included.
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-- The above copyright notice and this permission notice shall be
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-- included in all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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-- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
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-- LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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-- OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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-- WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWAR
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity de1 is
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entity de1 is
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port (
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port (
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-- //////////////////// Clock Input ////////////////////
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-- //////////////////// Clock Input ////////////////////
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CLOCK_24 : in std_logic_vector (1 downto 0);
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CLOCK_24 : in std_logic_vector (1 downto 0);
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CLOCK_27 : in std_logic_vector (1 downto 0);
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CLOCK_27 : in std_logic_vector (1 downto 0);
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CLOCK_50 : in std_logic;
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CLOCK_50 : in std_logic;
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EXT_CLOCK : in std_logic;
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EXT_CLOCK : in std_logic;
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-- //////////////////// Push Button ////////////////////
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-- //////////////////// Push Button ////////////////////
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KEY : in std_logic_vector(3 downto 0);
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KEY : in std_logic_vector(3 downto 0);
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-- //////////////////// DPDT Switch ////////////////////
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-- //////////////////// DPDT Switch ////////////////////
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SW : in std_logic_vector (9 downto 0);
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SW : in std_logic_vector (9 downto 0);
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-- //////////////////// 7-SEG Dispaly ////////////////////
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-- //////////////////// 7-SEG Dispaly ////////////////////
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HEX0 : out std_logic_vector (6 downto 0);
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HEX0 : out std_logic_vector (6 downto 0);
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HEX1 : out std_logic_vector (6 downto 0);
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HEX1 : out std_logic_vector (6 downto 0);
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HEX2 : out std_logic_vector (6 downto 0);
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HEX2 : out std_logic_vector (6 downto 0);
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HEX3 : out std_logic_vector (6 downto 0);
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HEX3 : out std_logic_vector (6 downto 0);
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-- //////////////////////// LED ////////////////////////
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-- //////////////////////// LED ////////////////////////
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LEDG : out std_logic_vector (7 downto 0);
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LEDG : out std_logic_vector (7 downto 0);
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LEDR : out std_logic_vector (9 downto 0);
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LEDR : out std_logic_vector (9 downto 0);
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-- //////////////////////// UART ////////////////////////
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-- //////////////////////// UART ////////////////////////
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UART_TXD : out std_logic;
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UART_TXD : out std_logic;
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UART_RXD : in std_logic;
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UART_RXD : in std_logic;
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-- ///////////////////// SDRAM Interface ////////////////
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-- ///////////////////// SDRAM Interface ////////////////
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DRAM_DQ : inout std_logic_vector (15 downto 0);
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DRAM_DQ : inout std_logic_vector (15 downto 0);
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DRAM_ADDR : out std_logic_vector (11 downto 0);
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DRAM_ADDR : out std_logic_vector (11 downto 0);
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DRAM_LDQM : out std_logic;
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DRAM_LDQM : out std_logic;
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DRAM_UDQM : out std_logic;
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DRAM_UDQM : out std_logic;
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DRAM_WE_N : out std_logic;
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DRAM_WE_N : out std_logic;
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DRAM_CAS_N : out std_logic;
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DRAM_CAS_N : out std_logic;
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DRAM_RAS_N : out std_logic;
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DRAM_RAS_N : out std_logic;
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DRAM_CS_N : out std_logic;
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DRAM_CS_N : out std_logic;
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DRAM_BA_0 : out std_logic;
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DRAM_BA_0 : out std_logic;
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DRAM_BA_1 : out std_logic;
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DRAM_BA_1 : out std_logic;
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DRAM_CLK : out std_logic;
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DRAM_CLK : out std_logic;
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DRAM_CKE : out std_logic;
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DRAM_CKE : out std_logic;
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-- //////////////////// Flash Interface ////////////////
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-- //////////////////// Flash Interface ////////////////
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FL_DQ : inout std_logic_vector (7 downto 0);
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FL_DQ : inout std_logic_vector (7 downto 0);
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FL_ADDR : out std_logic_vector (21 downto 0);
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FL_ADDR : out std_logic_vector (21 downto 0);
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FL_WE_N : out std_logic;
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FL_WE_N : out std_logic;
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FL_RST_N : out std_logic;
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FL_RST_N : out std_logic;
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FL_OE_N : out std_logic;
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FL_OE_N : out std_logic;
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FL_CE_N : out std_logic;
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FL_CE_N : out std_logic;
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-- //////////////////// SRAM Interface ////////////////
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-- //////////////////// SRAM Interface ////////////////
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SRAM_DQ : inout std_logic_vector (15 downto 0);
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SRAM_DQ : inout std_logic_vector (15 downto 0);
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SRAM_ADDR : out std_logic_vector (17 downto 0);
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SRAM_ADDR : out std_logic_vector (17 downto 0);
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SRAM_UB_N : out std_logic;
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SRAM_UB_N : out std_logic;
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SRAM_LB_N : out std_logic;
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SRAM_LB_N : out std_logic;
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SRAM_WE_N : out std_logic;
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SRAM_WE_N : out std_logic;
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SRAM_CE_N : out std_logic;
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SRAM_CE_N : out std_logic;
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SRAM_OE_N : out std_logic;
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SRAM_OE_N : out std_logic;
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-- //////////////////// SD_Card Interface ////////////////
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-- //////////////////// SD_Card Interface ////////////////
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SD_DAT : inout std_logic;
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SD_DAT : inout std_logic;
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SD_DAT3 : inout std_logic;
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SD_DAT3 : inout std_logic;
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SD_CMD : inout std_logic;
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SD_CMD : inout std_logic;
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SD_CLK : out std_logic;
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SD_CLK : out std_logic;
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-- //////////////////// USB JTAG link ////////////////////
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-- //////////////////// USB JTAG link ////////////////////
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TDI : in std_logic;
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TDI : in std_logic;
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TCK : in std_logic;
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TCK : in std_logic;
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TCS : in std_logic;
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TCS : in std_logic;
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TDO : out std_logic;
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TDO : out std_logic;
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-- //////////////////// I2C ////////////////////////////
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-- //////////////////// I2C ////////////////////////////
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I2C_SDAT : inout std_logic;
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I2C_SDAT : inout std_logic;
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I2C_SCLK : out std_logic;
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I2C_SCLK : out std_logic;
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-- //////////////////// PS2 ////////////////////////////
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-- //////////////////// PS2 ////////////////////////////
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PS2_DAT : in std_logic;
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PS2_DAT : in std_logic;
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PS2_CLK : in std_logic;
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PS2_CLK : in std_logic;
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-- //////////////////// VGA ////////////////////////////
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-- //////////////////// VGA ////////////////////////////
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VGA_HS : out std_logic;
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VGA_HS : out std_logic;
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VGA_VS : out std_logic;
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VGA_VS : out std_logic;
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VGA_R : out std_logic_vector (3 downto 0);
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VGA_R : out std_logic_vector (3 downto 0);
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VGA_G: out std_logic_vector (3 downto 0);
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VGA_G: out std_logic_vector (3 downto 0);
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VGA_B: out std_logic_vector (3 downto 0);
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VGA_B: out std_logic_vector (3 downto 0);
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-- //////////////// Audio CODEC ////////////////////////
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-- //////////////// Audio CODEC ////////////////////////
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AUD_ADCLRCK : inout std_logic;
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AUD_ADCLRCK : inout std_logic;
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AUD_ADCDAT : in std_logic;
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AUD_ADCDAT : in std_logic;
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AUD_DACLRCK : inout std_logic;
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AUD_DACLRCK : inout std_logic;
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AUD_DACDAT : out std_logic;
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AUD_DACDAT : out std_logic;
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AUD_BCLK : out std_logic;
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AUD_BCLK : out std_logic;
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AUD_XCK : out std_logic;
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AUD_XCK : out std_logic;
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-- //////////////////// GPIO ////////////////////////////
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-- //////////////////// GPIO ////////////////////////////
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GPIO_0 : inout std_logic_vector (35 downto 0);
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GPIO_0 : inout std_logic_vector (35 downto 0);
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GPIO_1 : inout std_logic_vector (35 downto 0)
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GPIO_1 : inout std_logic_vector (35 downto 0)
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);
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);
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end;
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end;
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architecture beh of de1 is
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architecture beh of de1 is
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signal reset : std_logic;
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signal reset : std_logic;
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signal pll_clk : std_logic;
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signal pll_clk : std_logic;
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signal pll_reset : std_logic := '0';
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signal pll_reset : std_logic := '0';
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signal pll_locked : std_logic;
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signal pll_locked : std_logic;
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signal spi_data_tx : std_logic_vector(31 downto 0);
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signal spi_data_tx : std_logic_vector(31 downto 0);
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signal spi_data_rx : std_logic_vector(31 downto 0);
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signal spi_data_rx : std_logic_vector(31 downto 0);
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signal spi_data_rx_en : std_logic;
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signal spi_data_rx_en : std_logic;
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signal running : std_logic := '0';
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signal running : std_logic := '0';
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signal overflow : std_logic := '0';
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signal overflow : std_logic := '0';
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signal found : std_logic := '0';
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signal found : std_logic := '0';
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signal spi_mosi : std_logic;
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signal spi_mosi : std_logic;
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signal spi_miso : std_logic;
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signal spi_miso : std_logic;
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signal spi_sck : std_logic;
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signal spi_sck : std_logic;
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signal spi_ss : std_logic;
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signal spi_ss : std_logic;
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signal pll_slow : std_logic;
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signal pll_slow : std_logic;
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component spi_slave
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component spi_slave
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port
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port
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(
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(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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mosi : in std_logic;
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mosi : in std_logic;
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miso : out std_logic;
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miso : out std_logic;
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sck : in std_logic;
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sck : in std_logic;
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ss : in std_logic;
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ss : in std_logic;
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data_rd : in std_logic_vector(31 downto 0);
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data_rd : in std_logic_vector(31 downto 0);
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data_wr : out std_logic_vector(31 downto 0);
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data_wr : out std_logic_vector(31 downto 0);
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data_wren : out std_logic
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data_wren : out std_logic
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);
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);
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end component;
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end component;
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component pll
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component pll
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PORT
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PORT
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(
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(
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areset : IN STD_LOGIC := '0';
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areset : IN STD_LOGIC := '0';
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inclk0 : IN STD_LOGIC := '0';
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inclk0 : IN STD_LOGIC := '0';
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c0 : OUT STD_LOGIC ;
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c0 : OUT STD_LOGIC ;
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c1 : out std_logic;
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c1 : out std_logic;
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locked : OUT STD_LOGIC
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locked : OUT STD_LOGIC
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);
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);
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end component;
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end component;
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component curl
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component curl
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port
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port
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(
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(
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clk : in std_logic;
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clk : in std_logic;
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clk_slow : in std_logic;
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clk_slow : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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spi_data_rx : in std_logic_vector(31 downto 0);
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spi_data_rx : in std_logic_vector(31 downto 0);
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spi_data_tx : out std_logic_vector(31 downto 0);
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spi_data_tx : out std_logic_vector(31 downto 0);
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spi_data_rxen : in std_logic;
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spi_data_rxen : in std_logic;
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overflow : out std_logic;
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overflow : out std_logic;
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running : out std_logic;
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running : out std_logic;
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found : out std_logic
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found : out std_logic
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);
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);
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end component;
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end component;
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begin
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begin
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pll0 : pll port map (
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pll0 : pll port map (
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areset => pll_reset,
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areset => pll_reset,
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inclk0 => CLOCK_50,
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inclk0 => CLOCK_50,
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c0 => pll_clk,
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c0 => pll_clk,
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c1 => pll_slow,
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c1 => pll_slow,
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locked => pll_locked
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locked => pll_locked
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);
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);
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spi0 : spi_slave port map (
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spi0 : spi_slave port map (
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clk => pll_slow,
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clk => pll_slow,
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reset => reset,
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reset => reset,
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mosi => spi_mosi,
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mosi => spi_mosi,
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miso => spi_miso,
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miso => spi_miso,
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sck => spi_sck,
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sck => spi_sck,
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ss => spi_ss,
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ss => spi_ss,
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data_rd => spi_data_tx,
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data_rd => spi_data_tx,
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data_wr => spi_data_rx,
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data_wr => spi_data_rx,
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data_wren => spi_data_rx_en
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data_wren => spi_data_rx_en
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);
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);
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curl0 : curl port map (
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curl0 : curl port map (
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clk => pll_clk,
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clk => pll_clk,
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reset => reset,
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reset => reset,
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clk_slow => pll_slow,
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clk_slow => pll_slow,
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spi_data_rx => spi_data_rx,
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spi_data_rx => spi_data_rx,
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spi_data_tx => spi_data_tx,
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spi_data_tx => spi_data_tx,
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spi_data_rxen => spi_data_rx_en,
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spi_data_rxen => spi_data_rx_en,
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overflow => overflow,
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overflow => overflow,
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running => running,
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running => running,
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found => found
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found => found
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);
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);
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-- disable all DE1 stuff
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-- disable all DE1 stuff
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DRAM_DQ <= (others => 'Z');
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DRAM_DQ <= (others => 'Z');
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FL_DQ <= (others => 'Z');
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FL_DQ <= (others => 'Z');
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SRAM_DQ <= (others => 'Z');
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SRAM_DQ <= (others => 'Z');
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SD_DAT <= 'Z';
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SD_DAT <= 'Z';
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I2C_SDAT <= 'Z';
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I2C_SDAT <= 'Z';
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GPIO_0 <= (others => 'Z');
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GPIO_0 <= (others => 'Z');
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GPIO_1 <= (others => 'Z');
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GPIO_1 <= (others => 'Z');
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LEDR <= "0" & "1" & spi_ss & spi_sck & spi_mosi & spi_miso & reset & overflow & found & running;
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LEDR <= "0" & "1" & spi_ss & spi_sck & spi_mosi & spi_miso & reset & overflow & found & running;
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LEDG <= (others => '0');
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LEDG <= (others => '0');
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AUD_BCLK <= '0';
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AUD_BCLK <= '0';
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AUD_DACLRCK <= '0';
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AUD_DACLRCK <= '0';
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AUD_ADCLRCK <= '0';
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AUD_ADCLRCK <= '0';
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AUD_XCK <= '0';
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AUD_XCK <= '0';
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SRAM_ADDR(17)<='0';
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SRAM_ADDR(17)<='0';
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reset <= not SW(0);
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reset <= not SW(0);
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spi_mosi <= GPIO_0(0);
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spi_mosi <= GPIO_0(0);
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spi_sck <= GPIO_0(2);
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spi_sck <= GPIO_0(2);
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spi_ss <= GPIO_0(3);
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spi_ss <= GPIO_0(3);
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-- all pins except one is input
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-- all pins except one is input
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GPIO_0(3 downto 0) <= "ZZ" & spi_miso & "Z";
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GPIO_0(3 downto 0) <= "ZZ" & spi_miso & "Z";
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end architecture;
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end architecture;
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