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-- IOTA Pearl Diver VHDL Port
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--
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-- Written 2018 by Thomas Pototschnig <microengineer18@gmail.com>
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--
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-- This source code is currently licensed under
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-- Attribution-NonCommercial 4.0 International (CC BY-NC 4.0)
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--
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-- http://www.microengineer.eu
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--
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-- If you like my project please consider a donation to
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--
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-- LLEYMHRKXWSPMGCMZFPKKTHSEMYJTNAZXSAYZGQUEXLXEEWPXUNWBFDWESOJVLHQHXOPQEYXGIRBYTLRWHMJAOSHUY
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--
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-- As soon as donations reach 1000MIOTA, everything will become
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-- GPL and open for any use - commercial included.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity spi_slave is
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entity spi_slave is
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port
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port
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(
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(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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mosi : in std_logic;
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mosi : in std_logic;
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miso : out std_logic;
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miso : out std_logic;
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sck : in std_logic;
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sck : in std_logic;
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ss : in std_logic;
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ss : in std_logic;
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data_rd : in std_logic_vector(31 downto 0);
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data_rd : in std_logic_vector(31 downto 0);
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data_wr : out std_logic_vector(31 downto 0);
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data_wr : out std_logic_vector(31 downto 0);
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data_wren : out std_logic
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data_wren : out std_logic
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);
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);
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end spi_slave;
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end spi_slave;
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architecture behv of spi_slave is
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architecture behv of spi_slave is
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signal sync_mosi : std_logic_vector(1 downto 0);
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signal sync_mosi : std_logic_vector(1 downto 0);
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signal sync_sck : std_logic_vector(1 downto 0);
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signal sync_sck : std_logic_vector(1 downto 0);
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signal sync_ss : std_logic_vector(1 downto 0);
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signal sync_ss : std_logic_vector(1 downto 0);
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begin
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begin
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process(clk)
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process(clk)
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variable cnt : integer range 0 to 32 := 0;
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variable cnt : integer range 0 to 32 := 0;
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variable iwren : std_logic;
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variable iwren : std_logic;
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variable i_miso : std_logic;
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variable i_miso : std_logic;
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variable i_shiftregister : std_logic_vector(31 downto 0);
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variable i_shiftregister : std_logic_vector(31 downto 0);
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if reset='1' then
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if reset='1' then
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cnt := 0;
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cnt := 0;
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data_wren <= '0';
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data_wren <= '0';
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iwren := '0';
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iwren := '0';
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else
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else
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iwren := '0';
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iwren := '0';
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sync_mosi <= sync_mosi(0) & mosi;
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sync_mosi <= sync_mosi(0) & mosi;
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sync_sck <= sync_sck(0) & sck;
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sync_sck <= sync_sck(0) & sck;
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sync_ss <= sync_ss(0) & ss;
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sync_ss <= sync_ss(0) & ss;
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case sync_ss is
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case sync_ss is
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when "11" =>
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when "11" =>
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i_shiftregister := data_rd;
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i_shiftregister := data_rd;
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cnt := 0;
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cnt := 0;
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-- i_flip := '0';
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-- i_flip := '0';
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when "10" =>
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when "10" =>
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miso <= i_shiftregister(31);
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miso <= i_shiftregister(31);
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when "01" =>
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when "01" =>
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cnt := 0;
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cnt := 0;
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iwren := '1';
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iwren := '1';
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data_wr <= i_shiftregister;
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data_wr <= i_shiftregister;
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when "00" =>
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when "00" =>
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case sync_sck is
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case sync_sck is
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when "01" =>
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when "01" =>
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i_shiftregister := i_shiftregister(30 downto 0) & sync_mosi(0);
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i_shiftregister := i_shiftregister(30 downto 0) & sync_mosi(0);
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cnt := cnt + 1;
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cnt := cnt + 1;
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when "10" =>
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when "10" =>
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miso <= i_shiftregister(31);
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miso <= i_shiftregister(31);
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when others =>
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when others =>
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end case;
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end case;
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when others =>
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when others =>
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end case;
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end case;
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data_wren <= iwren;
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data_wren <= iwren;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end behv;
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end behv;
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