/*
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/*
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Author: Sebastien Riou (acapola)
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Author: Sebastien Riou (acapola)
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Creation date: 19:57:35 10/31/2010
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Creation date: 19:57:35 10/31/2010
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$LastChangedDate: 2011-03-07 14:17:52 +0100 (Mon, 07 Mar 2011) $
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$LastChangedDate: 2011-04-17 23:31:29 +0200 (Sun, 17 Apr 2011) $
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$LastChangedBy: acapola $
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$LastChangedBy: acapola $
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$LastChangedRevision: 18 $
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$LastChangedRevision: 19 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/HalfDuplexUartIf.v $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/HalfDuplexUartIf.v $
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This file is under the BSD licence:
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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Copyright (c) 2011, Sebastien Riou
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All rights reserved.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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`default_nettype none
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`default_nettype none
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module HalfDuplexUartIf
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module HalfDuplexUartIf
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#(//parameters to override
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#(//parameters to override
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parameter DIVIDER_WIDTH = 1,
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parameter DIVIDER_WIDTH = 1,
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parameter CLOCK_PER_BIT_WIDTH = 13 //allow to support default speed of ISO7816
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parameter CLOCK_PER_BIT_WIDTH = 13 //allow to support default speed of ISO7816
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)
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)
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(
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(
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input wire nReset,
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input wire nReset,
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input wire clk,
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input wire clk,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire [7:0] dataIn,
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input wire [7:0] dataIn,
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input wire nWeDataIn,
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input wire nWeDataIn,
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input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
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input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
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input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
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input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
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input wire msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
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input wire msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
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output wire [7:0] dataOut,
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output wire [7:0] dataOut,
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input wire nCsDataOut,
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input wire nCsDataOut,
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output wire [7:0] statusOut,
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output wire [7:0] statusOut,
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input wire nCsStatusOut,
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input wire nCsStatusOut,
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input wire serialIn,
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input wire serialIn,
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output wire serialOut,
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output wire serialOut,
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output wire comClk
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output wire comClk
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);
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);
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reg [7:0] dataReg;
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reg [7:0] dataReg;
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// Inputs
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// Inputs
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wire [7:0] txData;
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wire [7:0] txData;
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reg txPending;
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reg txPending;
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wire ackFlags;
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wire ackFlags;
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// Outputs
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// Outputs
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wire [7:0] rxData;
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wire [7:0] rxData;
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wire overrunErrorFlag;
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wire overrunErrorFlag;
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wire dataOutReadyFlag;
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wire dataOutReadyFlag;
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wire frameErrorFlag;
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wire frameErrorFlag;
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wire txRun;
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wire txRun;
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wire endOfRx;
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wire endOfRx;
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wire rxRun;
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wire rxRun;
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wire rxStartBit;
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wire rxStartBit;
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wire txFull;
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wire txFull;
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wire isTx;
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wire isTx;
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wire rxFlagsSet = dataOutReadyFlag | overrunErrorFlag | frameErrorFlag;
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wire rxFlagsSet = dataOutReadyFlag | overrunErrorFlag | frameErrorFlag;
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reg bufferFull;
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reg bufferFull;
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reg [1:0] flagsReg;
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reg [1:0] flagsReg;
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assign txData = dataReg;
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assign txData = dataReg;
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assign dataOut=dataReg;
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assign dataOut=dataReg;
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assign statusOut[7:0]={txRun, txPending, rxRun, rxStartBit, isTx, flagsReg, bufferFull};
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assign statusOut[7:0]={txRun, txPending, rxRun, rxStartBit, isTx, flagsReg, bufferFull};
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reg waitTxFull0;//internal reg for managing bufferFull bit in Tx
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reg waitTxFull0;//internal reg for managing bufferFull bit in Tx
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assign ackFlags=~txPending & ~txRun & rxFlagsSet & ((bufferFull & ~nCsDataOut)| ~bufferFull);
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assign ackFlags=~txPending & ~txRun & rxFlagsSet & ((bufferFull & ~nCsDataOut)| ~bufferFull);
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always @(posedge clk, negedge nReset) begin
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always @(posedge clk, negedge nReset) begin
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if(~nReset) begin
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if(~nReset) begin
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bufferFull <= 1'b0;
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bufferFull <= 1'b0;
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flagsReg <= 1'b0;
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flagsReg <= 2'b00;
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txPending <= 1'b0;
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txPending <= 1'b0;
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end else begin
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end else begin
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if(ackFlags) begin
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if(ackFlags) begin
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dataReg <= rxData;
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dataReg <= rxData;
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flagsReg <= {overrunErrorFlag, frameErrorFlag};
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flagsReg <= {overrunErrorFlag, frameErrorFlag};
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if(rxFlagsSet)
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if(rxFlagsSet)
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bufferFull <= 1'b1;
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bufferFull <= 1'b1;
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else
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else
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bufferFull <= 1'b0;
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bufferFull <= 1'b0;
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end else if(txPending) begin
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end else if(txPending) begin
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if(waitTxFull0) begin
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if(waitTxFull0) begin
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if(~txFull)
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if(~txFull)
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waitTxFull0 <= 1'b0;
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waitTxFull0 <= 1'b0;
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end else if(txFull) begin//tx actually started, clear txPending and free buffer
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end else if(txFull) begin//tx actually started, clear txPending and free buffer
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txPending <= 1'b0;
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txPending <= 1'b0;
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bufferFull <= 1'b0; //buffer is empty
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bufferFull <= 1'b0; //buffer is empty
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end
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end
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end else if(~nCsDataOut) begin
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end else if(~nCsDataOut) begin
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bufferFull <= 1'b0;
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bufferFull <= 1'b0;
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end else if(~nWeDataIn) begin
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end else if(~nWeDataIn) begin
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dataReg <= dataIn;
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dataReg <= dataIn;
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bufferFull <= 1'b1;
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bufferFull <= 1'b1;
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txPending <= 1'b1;
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txPending <= 1'b1;
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waitTxFull0 <= txFull;
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waitTxFull0 <= txFull;
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end
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end
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end
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end
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end
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end
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wire endOfTx;
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wire endOfTx;
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BasicHalfDuplexUart #(
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BasicHalfDuplexUart #(
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.DIVIDER_WIDTH(DIVIDER_WIDTH),
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.DIVIDER_WIDTH(DIVIDER_WIDTH),
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.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH)
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.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH)
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)
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)
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uart (
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uart (
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.rxData(rxData),
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.rxData(rxData),
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.overrunErrorFlag(overrunErrorFlag),
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.overrunErrorFlag(overrunErrorFlag),
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.dataOutReadyFlag(dataOutReadyFlag),
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.dataOutReadyFlag(dataOutReadyFlag),
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.frameErrorFlag(frameErrorFlag),
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.frameErrorFlag(frameErrorFlag),
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.txRun(txRun),
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.txRun(txRun),
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.endOfRx(endOfRx),
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.endOfRx(endOfRx),
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.endOfTx(endOfTx),
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.endOfTx(endOfTx),
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.rxRun(rxRun),
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.rxRun(rxRun),
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.rxStartBit(rxStartBit),
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.rxStartBit(rxStartBit),
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.txFull(txFull),
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.txFull(txFull),
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.isTx(isTx),
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.isTx(isTx),
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.serialIn(serialIn),
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.serialIn(serialIn),
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.serialOut(serialOut),
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.serialOut(serialOut),
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.comClk(comClk),
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.comClk(comClk),
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.txData(txData),
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.txData(txData),
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.clocksPerBit(clocksPerBit),
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.clocksPerBit(clocksPerBit),
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.stopBit2(stopBit2),
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.stopBit2(stopBit2),
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.oddParity(oddParity),
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.oddParity(oddParity),
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.msbFirst(msbFirst),
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.msbFirst(msbFirst),
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.startTx(txPending),
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.startTx(txPending),
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.ackFlags(ackFlags),
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.ackFlags(ackFlags),
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.clkPerCycle(clkPerCycle),
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.clkPerCycle(clkPerCycle),
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.clk(clk),
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.clk(clk),
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.nReset(nReset)
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.nReset(nReset)
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);
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);
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endmodule
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endmodule
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`default_nettype wire
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`default_nettype wire
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