/*
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/*
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Author: Sebastien Riou (acapola)
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Author: Sebastien Riou (acapola)
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Creation date: 17:16:40 01/09/2011
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Creation date: 17:16:40 01/09/2011
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$LastChangedDate: 2011-02-18 15:23:07 +0100 (Fri, 18 Feb 2011) $
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$LastChangedDate: 2011-03-07 14:17:52 +0100 (Mon, 07 Mar 2011) $
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$LastChangedBy: acapola $
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$LastChangedBy: acapola $
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$LastChangedRevision: 17 $
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$LastChangedRevision: 18 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/Iso7816_3_Master.v $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/Iso7816_3_Master.v $
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This file is under the BSD licence:
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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Copyright (c) 2011, Sebastien Riou
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All rights reserved.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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`default_nettype none
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`default_nettype none
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module Iso7816_3_Master(
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module Iso7816_3_Master(
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input wire nReset,
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input wire nReset,
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input wire clk,
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input wire clk,
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input wire [15:0] clkPerCycle,//not supported yet
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input wire [15:0] clkPerCycle,//not supported yet
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input wire startActivation,//Starts activation sequence
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input wire startActivation,//Starts activation sequence
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input wire startDeactivation,//Starts deactivation sequence
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input wire startDeactivation,//Starts deactivation sequence
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input wire [7:0] dataIn,
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input wire [7:0] dataIn,
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input wire nWeDataIn,
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input wire nWeDataIn,
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input wire [12:0] cyclesPerEtu,
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input wire [12:0] cyclesPerEtu,
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output reg [7:0] dataOut,
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output reg [7:0] dataOut,
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input wire nCsDataOut,
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input wire nCsDataOut,
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output wire [7:0] statusOut,
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output wire [7:0] statusOut,
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input wire nCsStatusOut,
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input wire nCsStatusOut,
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output reg isActivated,//set to high by activation sequence, set to low by deactivation sequence
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output reg isActivated,//set to high by activation sequence, set to low by deactivation sequence
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output wire useIndirectConvention,
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output wire useIndirectConvention,
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output wire tsError,//high if TS character is wrong
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output wire tsError,//high if TS character is wrong
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output wire tsReceived,
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output wire tsReceived,
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output wire atrIsEarly,//high if TS received before 400 cycles after reset release
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output wire atrIsEarly,//high if TS received before 400 cycles after reset release
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output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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//ISO7816 signals
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//ISO7816 signals
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inout wire isoSio,
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//inout wire isoSio,//not synthesisable on FPGA :-S
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output wire isTx,
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input wire isoSioIn,
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output wire isoSioOut,
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output wire isoClk,
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output wire isoClk,
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output reg isoReset,
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output reg isoReset,
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output reg isoVdd
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output reg isoVdd
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);
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);
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wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
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wire txRun,txPending, rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;
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assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
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assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
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wire serialOut;
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//wire serialOut;
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assign isoSio = isTx ? serialOut : 1'bz;
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//not synthesisable on FPGA :-S
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pullup(isoSio);
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//assign isoSio = isTx ? serialOut : 1'bz;
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//pullup(isoSio);
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wire comClk;
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wire comClk;
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wire stopBit2=1'b1;//0: 1 stop bit, 1: 2 stop bits
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wire stopBit2=1'b1;//0: 1 stop bit, 1: 2 stop bits
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wire msbFirst = useIndirectConvention;//if 1, bits order is: startBit, b7, b6, b5...b0, parity
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wire msbFirst = useIndirectConvention;//if 1, bits order is: startBit, b7, b6, b5...b0, parity
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wire oddParity = 1'b0;//if 1, parity bit is such that data+parity have an odd number of 1
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wire oddParity = 1'b0;//if 1, parity bit is such that data+parity have an odd number of 1
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wire sioHighValue = ~useIndirectConvention;//apply only to data bits
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wire sioHighValue = ~useIndirectConvention;//apply only to data bits
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wire [7:0] uart_dataOut;
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wire [7:0] uart_dataOut;
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wire [7:0] uart_dataIn = sioHighValue ? dataIn : ~dataIn;
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wire [7:0] uart_dataIn = sioHighValue ? dataIn : ~dataIn;
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always @(*) dataOut = sioHighValue ? uart_dataOut : ~uart_dataOut;
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always @(*) dataOut = sioHighValue ? uart_dataOut : ~uart_dataOut;
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HalfDuplexUartIf #(
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HalfDuplexUartIf #(
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.DIVIDER_WIDTH(1'b1),
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.DIVIDER_WIDTH(1'b1),
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.CLOCK_PER_BIT_WIDTH(4'd13)
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.CLOCK_PER_BIT_WIDTH(4'd13)
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)
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)
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uart (
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uart (
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.nReset(nReset),
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.nReset(nReset),
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.clk(clk),
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.clk(clk),
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.clkPerCycle(1'b0),
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.clkPerCycle(1'b0),
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.dataIn(uart_dataIn),
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.dataIn(uart_dataIn),
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.nWeDataIn(nWeDataIn),
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.nWeDataIn(nWeDataIn),
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.clocksPerBit(cyclesPerEtu),
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.clocksPerBit(cyclesPerEtu),
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.stopBit2(stopBit2),
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.stopBit2(stopBit2),
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.oddParity(oddParity),
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.oddParity(oddParity),
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.msbFirst(msbFirst),
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.msbFirst(msbFirst),
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.dataOut(uart_dataOut),
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.dataOut(uart_dataOut),
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.nCsDataOut(nCsDataOut),
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.nCsDataOut(nCsDataOut),
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.statusOut(statusOut),
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.statusOut(statusOut),
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.nCsStatusOut(nCsStatusOut),
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.nCsStatusOut(nCsStatusOut),
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.serialIn(isoSio),
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.serialIn(isoSioIn),
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.serialOut(serialOut),
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.serialOut(isoSioOut),
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.comClk(comClk)
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.comClk(comClk)
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);
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);
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reg isoClkEn;
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reg isoClkEn;
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assign isoClk = isoClkEn ? comClk : 1'b0;
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assign isoClk = isoClkEn ? comClk : 1'b0;
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reg [16:0] resetCnt;
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reg [16:0] resetCnt;
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reg waitTs;
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reg waitTs;
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assign tsReceived = ~waitTs;
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assign tsReceived = ~waitTs;
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reg [7:0] ts;
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reg [7:0] ts;
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assign atrIsEarly = ~waitTs & (resetCnt<(16'h100+16'd400));
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assign atrIsEarly = ~waitTs & (resetCnt<(16'h100+16'd400));
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assign atrIsLate = resetCnt>(16'h100+16'd40000);
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assign atrIsLate = resetCnt>(16'h100+16'd40000);
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assign useIndirectConvention = ~waitTs & (ts==8'h3F);
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assign useIndirectConvention = ~waitTs & (ts==8'h3F);
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assign tsError = ~waitTs & (ts!=8'h3B) & (ts!=8'h3F);
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assign tsError = ~waitTs & (ts!=8'h3B) & (ts!=8'h3F);
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always @(posedge comClk, negedge nReset) begin
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always @(posedge comClk, negedge nReset) begin
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if(~nReset) begin
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if(~nReset) begin
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isoClkEn <= 1'b0;
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isoClkEn <= 1'b0;
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resetCnt<=16'b0;
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resetCnt<=16'b0;
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waitTs<=1'b1;
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waitTs<=1'b1;
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isoReset <= 1'b0;
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isoReset <= 1'b0;
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isoVdd <= 1'b0;
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isoVdd <= 1'b0;
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isActivated <= 1'b0;
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isActivated <= 1'b0;
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end else if(isActivated) begin
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end else if(isActivated) begin
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if(waitTs) begin
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if(waitTs) begin
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if(statusOut[0]) begin
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if(statusOut[0]) begin
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waitTs<=1'b0;
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waitTs<=1'b0;
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case(dataOut)
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case(dataOut)
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8'h3B: ts<=dataOut;
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8'h3B: ts<=dataOut;
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8'h03: ts<=8'h3F;//03 is 3F written LSB first and complemented
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8'h03: ts<=8'h3F;//03 is 3F written LSB first and complemented
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default: ts<=dataOut;
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default: ts<=dataOut;
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endcase
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endcase
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end
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end
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resetCnt<=resetCnt+1;
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resetCnt<=resetCnt+1'b1;
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end
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end
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if(startDeactivation) begin
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if(startDeactivation) begin
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isoVdd <= 1'b0;
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isoVdd <= 1'b0;
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isoClkEn <= 1'b0;
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isoClkEn <= 1'b0;
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isoReset <= 1'b0;
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isoReset <= 1'b0;
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resetCnt<=16'b0;
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resetCnt<=16'b0;
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isActivated <= 1'b0;
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isActivated <= 1'b0;
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end
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end
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end else begin
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end else begin
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if(startActivation) begin
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if(startActivation) begin
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waitTs <= 1'b1;
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waitTs <= 1'b1;
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isoVdd <= 1'b1;
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isoVdd <= 1'b1;
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isoClkEn <= 1'b1;
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isoClkEn <= 1'b1;
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if(16'h100 == resetCnt) begin
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if(16'h100 == resetCnt) begin
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isActivated <=1'b1;
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isActivated <=1'b1;
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isoReset <=1'b1;
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isoReset <=1'b1;
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end else
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end else
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resetCnt<=resetCnt + 1;
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resetCnt<=resetCnt + 1'b1;
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end else begin
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end else begin
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resetCnt<=16'b0;
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resetCnt<=16'b0;
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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`default_nettype wire
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`default_nettype wire
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