`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`default_nettype none
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 17:16:40 01/09/2011
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// Create Date: 17:16:40 01/09/2011
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// Design Name:
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// Design Name:
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// Module Name: Iso7816_3_Master
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// Module Name: Iso7816_3_Master
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module Iso7816_3_Master(
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module Iso7816_3_Master(
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input wire nReset,
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input wire nReset,
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input wire clk,
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input wire clk,
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input wire [15:0] clkPerCycle,//not supported yet
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input wire [15:0] clkPerCycle,//not supported yet
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input wire startActivation,//Starts activation sequence
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input wire startActivation,//Starts activation sequence
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input wire startDeactivation,//Starts deactivation sequence
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input wire startDeactivation,//Starts deactivation sequence
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input wire [7:0] dataIn,
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input wire [7:0] dataIn,
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input wire nWeDataIn,
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input wire nWeDataIn,
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input wire [12:0] cyclePerEtu,
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input wire [12:0] cyclePerEtu,
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output wire [7:0] dataOut,
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output wire [7:0] dataOut,
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input wire nCsDataOut,
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input wire nCsDataOut,
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output wire [7:0] statusOut,
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output wire [7:0] statusOut,
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input wire nCsStatusOut,
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input wire nCsStatusOut,
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output reg isActivated,//set to high by activation sequence, set to low by deactivation sequence
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output reg isActivated,//set to high by activation sequence, set to low by deactivation sequence
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output wire useIndirectConvention,
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output wire useIndirectConvention,
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output wire tsError,//high if TS character is wrong
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output wire tsError,//high if TS character is wrong
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output wire tsReceived,
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output wire tsReceived,
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output wire atrIsEarly,//high if TS received before 400 cycles after reset release
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output wire atrIsEarly,//high if TS received before 400 cycles after reset release
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output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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//ISO7816 signals
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//ISO7816 signals
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inout wire isoSio,
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inout wire isoSio,
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output wire isoClk,
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output wire isoClk,
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output reg isoReset,
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output reg isoReset,
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output reg isoVdd
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output reg isoVdd
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);
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);
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wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
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wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
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assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
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assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
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wire serialOut;
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wire serialOut;
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assign isoSio = isTx ? serialOut : 1'bz;
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assign isoSio = isTx ? serialOut : 1'bz;
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pullup(isoSio);
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pullup(isoSio);
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wire comClk;
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wire comClk;
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HalfDuplexUartIf uart (
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HalfDuplexUartIf uart (
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.nReset(nReset),
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.nReset(nReset),
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.clk(clk),
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.clk(clk),
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.clkPerCycle(1'b0),
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.clkPerCycle(1'b0),
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.dataIn(dataIn),
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.dataIn(dataIn),
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.nWeDataIn(nWeDataIn),
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.nWeDataIn(nWeDataIn),
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.dataOut(dataOut),
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.dataOut(dataOut),
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.nCsDataOut(nCsDataOut),
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.nCsDataOut(nCsDataOut),
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.statusOut(statusOut),
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.statusOut(statusOut),
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.nCsStatusOut(nCsStatusOut),
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.nCsStatusOut(nCsStatusOut),
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.serialIn(isoSio),
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.serialIn(isoSio),
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.serialOut(serialOut),
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.serialOut(serialOut),
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.comClk(comClk)
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.comClk(comClk)
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);
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);
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reg isoClkEn;
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reg isoClkEn;
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assign isoClk = isoClkEn ? comClk : 1'b0;
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assign isoClk = isoClkEn ? comClk : 1'b0;
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reg [16:0] resetCnt;
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reg [16:0] resetCnt;
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reg waitTs;
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reg waitTs;
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assign tsReceived = ~waitTs;
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assign tsReceived = ~waitTs;
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reg [7:0] ts;
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reg [7:0] ts;
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assign atrIsEarly = ~waitTs & (resetCnt<(16'h100+16'd400));
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assign atrIsEarly = ~waitTs & (resetCnt<(16'h100+16'd400));
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assign atrIsLate = resetCnt>(16'h100+16'd40000);
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assign atrIsLate = resetCnt>(16'h100+16'd40000);
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assign useIndirectConvention = ~waitTs & (ts==8'h3F);
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assign useIndirectConvention = ~waitTs & (ts==8'h3F);
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assign tsError = ~waitTs & (ts!=8'h3B) & ~useIndirectConvention;
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assign tsError = ~waitTs & (ts!=8'h3B) & ~useIndirectConvention;
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always @(posedge comClk, negedge nReset) begin
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always @(posedge comClk, negedge nReset) begin
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if(~nReset) begin
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if(~nReset) begin
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isoClkEn <= 1'b0;
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isoClkEn <= 1'b0;
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resetCnt<=16'b0;
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resetCnt<=16'b0;
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waitTs<=1'b1;
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waitTs<=1'b1;
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isoReset <= 1'b0;
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isoReset <= 1'b0;
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isoVdd <= 1'b0;
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isoVdd <= 1'b0;
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isActivated <= 1'b0;
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isActivated <= 1'b0;
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end else if(isActivated) begin
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end else if(isActivated) begin
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if(waitTs) begin
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if(waitTs) begin
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if(statusOut[0]) begin
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if(statusOut[0]) begin
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waitTs<=1'b0;
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waitTs<=1'b0;
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ts<=dataOut;
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ts<=dataOut;
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end
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end
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resetCnt<=resetCnt+1;
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resetCnt<=resetCnt+1;
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end
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end
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if(startDeactivation) begin
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if(startDeactivation) begin
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isoVdd <= 1'b0;
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isoVdd <= 1'b0;
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isoClkEn <= 1'b0;
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isoClkEn <= 1'b0;
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isoReset <= 1'b0;
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isoReset <= 1'b0;
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resetCnt<=16'b0;
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resetCnt<=16'b0;
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isActivated <= 1'b0;
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isActivated <= 1'b0;
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end
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end
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end else begin
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end else begin
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if(startActivation) begin
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if(startActivation) begin
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waitTs <= 1'b1;
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waitTs <= 1'b1;
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isoVdd <= 1'b1;
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isoVdd <= 1'b1;
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isoClkEn <= 1'b1;
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isoClkEn <= 1'b1;
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if(16'h100 == resetCnt) begin
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if(16'h100 == resetCnt) begin
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isActivated <=1'b1;
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isActivated <=1'b1;
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isoReset <=1'b1;
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isoReset <=1'b1;
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end else
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end else
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resetCnt<=resetCnt + 1;
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resetCnt<=resetCnt + 1;
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end else begin
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end else begin
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resetCnt<=16'b0;
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resetCnt<=16'b0;
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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