OpenCores
URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [sources/] [RxCore.v] - Diff between revs 5 and 7

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 5 Rev 7
`timescale 1ns / 1ps
`timescale 1ns / 1ps
`default_nettype none
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Company: 
// Engineer: Sebastien Riou
// Engineer: Sebastien Riou
// 
// 
// Create Date:    23:57:02 08/31/2010 
// Create Date:    23:57:02 08/31/2010 
// Design Name: 
// Design Name: 
// Module Name:    RxCore 
// Module Name:    RxCore 
// Project Name: 
// Project Name: 
// Target Devices: 
// Target Devices: 
// Tool versions: 
// Tool versions: 
// Description: 
// Description: 
//
//
// Dependencies: 
// Dependencies: 
//
//
// Revision: 
// Revision: 
// Revision 0.01 - File Created
// Revision 0.01 - File Created
// Additional Comments: 
// Additional Comments: 
//
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
module RxCore(
module RxCore(
   output reg [7:0] dataOut,
   output reg [7:0] dataOut,
   output reg overrunErrorFlag, //new data has been received before dataOut was read
   output reg overrunErrorFlag, //new data has been received before dataOut was read
   output reg dataOutReadyFlag, //new data available
   output reg dataOutReadyFlag, //new data available
   output reg frameErrorFlag,           //bad parity or bad stop bits
   output reg frameErrorFlag,           //bad parity or bad stop bits
   output reg endOfRx,                          //one cycle pulse: 1 during last cycle of last stop bit
   output reg endOfRx,                          //one cycle pulse: 1 during last cycle of last stop bit
   output reg run,                                      //rx is definitely started, one of the three flag will be set
   output reg run,                                      //rx is definitely started, one of the three flag will be set
   output wire startBit,                        //rx is started, but we don't know yet if real rx or just a glitch
   output wire startBit,                        //rx is started, but we don't know yet if real rx or just a glitch
        output wire stopBit,                            //rx is over but still in stop bits
        output reg stopBit,                             //rx is over but still in stop bits
        input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
        input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
        input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
        input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
        input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
        input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
   input wire msbFirst,  //if 1, bits order is: startBit, b7, b6, b5...b0, parity
   input wire msbFirst,  //if 1, bits order is: startBit, b7, b6, b5...b0, parity
        input wire ackFlags,
        input wire ackFlags,
        input wire serialIn,
        input wire serialIn,
        input wire clk,
        input wire clk,
   input wire nReset,
   input wire nReset,
        //to connect to an instance of Counter.v (see RxCoreSelfContained.v for example)
        //to connect to an instance of Counter.v (see RxCoreSelfContained.v for example)
        output reg [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounterCompare,
        output reg [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounterCompare,
        output reg bitClocksCounterInc,
        output reg bitClocksCounterInc,
        output reg bitClocksCounterClear,
        output reg bitClocksCounterClear,
        output wire bitClocksCounterInitVal,
        output wire bitClocksCounterInitVal,
   input wire bitClocksCounterEarlyMatch,
   input wire bitClocksCounterEarlyMatch,
        input wire bitClocksCounterMatch
        input wire bitClocksCounterMatch,
 
        input wire [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounter
    );
    );
 
 
//parameters to override
//parameters to override
parameter CLOCK_PER_BIT_WIDTH = 13;     //allow to support default speed of ISO7816
parameter CLOCK_PER_BIT_WIDTH = 13;     //allow to support default speed of ISO7816
 
parameter PRECISE_STOP_BIT = 0; //if 1, stopBit signal goes high exactly at start of stop bit instead of middle of parity bit
 
 
//default conventions
//default conventions
parameter START_BIT = 1'b0;
parameter START_BIT = 1'b0;
parameter STOP_BIT1 = 1'b1;
parameter STOP_BIT1 = 1'b1;
parameter STOP_BIT2 = 1'b1;
parameter STOP_BIT2 = 1'b1;
 
 
//constant definition for states
//constant definition for states
localparam IDLE_STATE =         3'b000;
localparam IDLE_STATE =         3'b000;
localparam START_STATE =        3'b001;
localparam START_STATE =        3'b001;
localparam DATA_STATE =         3'b011;
localparam DATA_STATE =         3'b011;
localparam PARITY_STATE =       3'b010;
localparam PARITY_STATE =       3'b010;
localparam STOP1_STATE =        3'b110;
localparam STOP1_STATE =        3'b110;
localparam STOP2_STATE =        3'b111;
localparam STOP2_STATE =        3'b111;
localparam END_STATE =          3'b101;
localparam END_STATE =          3'b101;
localparam END2_STATE =    3'b100;
localparam END2_STATE =    3'b100;
 
 
localparam IDLE_BIT = ~START_BIT;
localparam IDLE_BIT = ~START_BIT;
 
 
reg [2:0] nextState;
reg [2:0] nextState;
 
 
reg [2:0] bitCounter;
reg [2:0] bitCounter;
wire [2:0] bitIndex = msbFirst ? 7-bitCounter : bitCounter;
wire [2:0] bitIndex = msbFirst ? 7-bitCounter : bitCounter;
reg parityBit;
reg parityBit;
 
 
wire internalIn;
wire internalIn;
wire parityError;
wire parityError;
 
 
assign startBit = (nextState == START_STATE);
assign startBit = (nextState == START_STATE);
assign stopBit = (nextState == STOP1_STATE) | (nextState == STOP2_STATE);
//assign stopBit = (nextState == STOP1_STATE) | (nextState == STOP2_STATE);
assign internalIn = serialIn;
assign internalIn = serialIn;
assign parityError= parityBit ^ internalIn ^ 1'b1;
assign parityError= parityBit ^ internalIn ^ 1'b1;
reg flagsSet;
reg flagsSet;
 
 
assign bitClocksCounterInitVal=(nextState==IDLE_STATE);
assign bitClocksCounterInitVal=(nextState==IDLE_STATE);
always @(nextState, clocksPerBit, run, bitClocksCounterMatch) begin
always @(nextState, clocksPerBit, run, bitClocksCounterMatch) begin
        case(nextState)
        case(nextState)
                IDLE_STATE: begin
                IDLE_STATE: begin
                        bitClocksCounterCompare = (clocksPerBit/2);
                        bitClocksCounterCompare = (clocksPerBit/2);
                        bitClocksCounterInc = run & ~bitClocksCounterMatch;//stop when reach 0
                        bitClocksCounterInc = run & ~bitClocksCounterMatch;//stop when reach 0
                        bitClocksCounterClear = ~run;
                        bitClocksCounterClear = ~run;
                end
                end
                START_STATE: begin
                START_STATE: begin
                        bitClocksCounterCompare = (clocksPerBit/2);
                        bitClocksCounterCompare = (clocksPerBit/2);
                        bitClocksCounterInc = 1;
                        bitClocksCounterInc = 1;
                        bitClocksCounterClear = 0;
                        bitClocksCounterClear = 0;
                end
                end
                STOP2_STATE: begin
                STOP2_STATE: begin
         //make the rx operation is one cycle shorter, 
         //make the rx operation is one cycle shorter, 
         //since we detect the start bit at least one cycle later it starts.
         //since we detect the start bit at least one cycle later it starts.
                        bitClocksCounterCompare = clocksPerBit-1;
                        bitClocksCounterCompare = clocksPerBit-1;
                        bitClocksCounterInc = 1;
                        bitClocksCounterInc = 1;
                        bitClocksCounterClear = 0;
                        bitClocksCounterClear = 0;
                end
                end
                default: begin
                default: begin
                        bitClocksCounterCompare = clocksPerBit;
                        bitClocksCounterCompare = clocksPerBit;
                        bitClocksCounterInc = 1;
                        bitClocksCounterInc = 1;
                        bitClocksCounterClear = 0;
                        bitClocksCounterClear = 0;
                end
                end
        endcase
        endcase
end
end
 
 
always @(posedge clk, negedge nReset) begin
always @(posedge clk, negedge nReset) begin
        if(~nReset) begin
        if(~nReset) begin
                nextState <= #1 IDLE_STATE;
                nextState <= #1 IDLE_STATE;
                bitCounter <= #1 0;
                bitCounter <= #1 0;
                parityBit <= #1 0;
                parityBit <= #1 0;
                overrunErrorFlag <= #1 0;
                overrunErrorFlag <= #1 0;
                dataOutReadyFlag <= #1 0;
                dataOutReadyFlag <= #1 0;
                frameErrorFlag <= #1 0;
                frameErrorFlag <= #1 0;
                run <= #1 0;
                run <= #1 0;
      endOfRx <= #1 0;
      endOfRx <= #1 0;
 
                stopBit<= #1 0;
        end else begin
        end else begin
                case(nextState)
                case(nextState)
                        IDLE_STATE: begin
                        IDLE_STATE: begin
                                if(bitClocksCounterEarlyMatch)
                                if(bitClocksCounterEarlyMatch)
               endOfRx <= #1 1'b1;
               endOfRx <= #1 1'b1;
            if(bitClocksCounterMatch)
            if(bitClocksCounterMatch) begin
               endOfRx <= #1 0;
               endOfRx <= #1 0;
 
                                        stopBit <= #1 0;
 
                                end
            if(ackFlags) begin
            if(ackFlags) begin
                                        //overrunErrorFlag is auto cleared at PARITY_STATE
                                        //overrunErrorFlag is auto cleared at PARITY_STATE
                                        //meanwhile, it prevent dataOutReadyFlag to be set by the termination of the lost byte
                                        //meanwhile, it prevent dataOutReadyFlag to be set by the termination of the lost byte
                                        dataOutReadyFlag <= #1 0;
                                        dataOutReadyFlag <= #1 0;
                                        frameErrorFlag <= #1 0;
                                        frameErrorFlag <= #1 0;
                                end
                                end
                                if(START_BIT == internalIn) begin
                                if(START_BIT == internalIn) begin
                                        if(frameErrorFlag | overrunErrorFlag) begin
                                        if(frameErrorFlag | overrunErrorFlag) begin
                                                //wait clear from outside
                                                //wait clear from outside
                                                if(bitClocksCounterMatch) begin
                                                if(bitClocksCounterMatch) begin
                     //endOfRx <= #1 0;
                     //endOfRx <= #1 0;
                                                        run <= #1 0;
                                                        run <= #1 0;
                  end
                  end
                                        end else begin
                                        end else begin
                                                parityBit <= #1 oddParity;
                                                parityBit <= #1 oddParity;
                                                run <= #1 0;
                                                run <= #1 0;
                                                nextState <= #1 START_STATE;
                                                nextState <= #1 START_STATE;
                                        end
                                        end
                                end else begin
                                end else begin
                                        if(bitClocksCounterMatch) begin
                                        if(bitClocksCounterMatch) begin
                  //endOfRx <= #1 0;
                  //endOfRx <= #1 0;
                                                run <= #1 0;
                                                run <= #1 0;
               end
               end
                                end
                                end
                        end
                        end
                        START_STATE: begin
                        START_STATE: begin
                                if(ackFlags) begin
                                if(ackFlags) begin
                                        dataOutReadyFlag <= #1 0;
                                        dataOutReadyFlag <= #1 0;
                                        frameErrorFlag <= #1 0;
                                        frameErrorFlag <= #1 0;
                                end
                                end
                                if(bitClocksCounterMatch) begin
                                if(bitClocksCounterMatch) begin
                                        if(START_BIT != internalIn) begin
                                        if(START_BIT != internalIn) begin
                                                nextState <= #1 IDLE_STATE;
                                                nextState <= #1 IDLE_STATE;
                                        end else begin
                                        end else begin
                                                run <= #1 1;
                                                run <= #1 1;
                                                nextState <= #1 DATA_STATE;
                                                nextState <= #1 DATA_STATE;
                                        end
                                        end
                                end
                                end
                        end
                        end
                        DATA_STATE: begin
                        DATA_STATE: begin
                                if(ackFlags) begin
                                if(ackFlags) begin
                                        dataOutReadyFlag <= #1 0;
                                        dataOutReadyFlag <= #1 0;
                                        frameErrorFlag <= #1 0;
                                        frameErrorFlag <= #1 0;
                                end
                                end
                                if(bitClocksCounterMatch) begin
                                if(bitClocksCounterMatch) begin
                                        if(dataOutReadyFlag) begin
                                        if(dataOutReadyFlag) begin
                                                overrunErrorFlag <= #1 1;
                                                overrunErrorFlag <= #1 1;
                                        end else
                                        end else
                                                dataOut[bitIndex] <= #1 internalIn;
                                                dataOut[bitIndex] <= #1 internalIn;
                                        parityBit <= #1 parityBit ^ internalIn;
                                        parityBit <= #1 parityBit ^ internalIn;
                                        bitCounter <= #1 (bitCounter + 1'b1) & 3'b111;
                                        bitCounter <= #1 (bitCounter + 1'b1) & 3'b111;
                                        if(bitCounter == 7)
                                        if(bitCounter == 7)
                                                nextState <= #1 PARITY_STATE;
                                                nextState <= #1 PARITY_STATE;
                                end
                                end
                        end
                        end
                        PARITY_STATE: begin
                        PARITY_STATE: begin
                                if(bitClocksCounterMatch) begin
                                if(bitClocksCounterMatch) begin
                                        if(~overrunErrorFlag) begin
                                        if(~overrunErrorFlag) begin
                                                frameErrorFlag <= #1 parityError;
                                                frameErrorFlag <= #1 parityError;
                                                dataOutReadyFlag <= #1 ~parityError;
                                                dataOutReadyFlag <= #1 ~parityError;
                                        end else if(ackFlags) begin
                                        end else if(ackFlags) begin
                                                frameErrorFlag <= #1 0;
                                                frameErrorFlag <= #1 0;
                                        end
                                        end
                                        flagsSet=1;
                                        flagsSet=1;
 
                                        if(PRECISE_STOP_BIT==0) stopBit <= #1 1;
                                        if(stopBit2)
                                        if(stopBit2)
                                                nextState <= #1 STOP1_STATE;
                                                nextState <= #1 STOP1_STATE;
                                        else
                                        else
                                                nextState <= #1 STOP2_STATE;
                                                nextState <= #1 STOP2_STATE;
                                end else if(ackFlags) begin
                                end else if(ackFlags) begin
                                        dataOutReadyFlag <= #1 0;
                                        dataOutReadyFlag <= #1 0;
                                        frameErrorFlag <= #1 0;
                                        frameErrorFlag <= #1 0;
                                end
                                end
                        end
                        end
                        STOP1_STATE: begin
                        STOP1_STATE: begin
                                if(ackFlags) begin
                                if(ackFlags) begin
                                        dataOutReadyFlag <= #1 0;
                                        dataOutReadyFlag <= #1 0;
                                end
                                end
                                if(bitClocksCounterMatch) begin
                                if(bitClocksCounterMatch) begin
                                        if(STOP_BIT1 != internalIn) begin
                                        if(STOP_BIT1 != internalIn) begin
                                                frameErrorFlag <= #1 parityError;
                                                frameErrorFlag <= #1 parityError;
                                        end else if(ackFlags) begin
                                        end else if(ackFlags) begin
                                                frameErrorFlag <= #1 0;
                                                frameErrorFlag <= #1 0;
                                        end
                                        end
                                        nextState <= #1 STOP2_STATE;
                                        nextState <= #1 STOP2_STATE;
                                end else if(ackFlags) begin
                                end else if(ackFlags) begin
                                        frameErrorFlag <= #1 0;
                                        frameErrorFlag <= #1 0;
                                end
                                end
 
                                if(PRECISE_STOP_BIT!=0) begin
 
                                        if(bitClocksCounter==(bitClocksCounterCompare/2)) begin
 
                                                stopBit <= #1 1;
 
                                        end
 
                                end
                        end
                        end
                        STOP2_STATE: begin
                        STOP2_STATE: begin
                                if(ackFlags) begin
                                if(ackFlags) begin
                                        dataOutReadyFlag <= #1 0;
                                        dataOutReadyFlag <= #1 0;
                                end
                                end
            if(bitClocksCounterMatch) begin
            if(bitClocksCounterMatch) begin
                                        if(STOP_BIT2 != internalIn) begin
                                        if(STOP_BIT2 != internalIn) begin
                                                frameErrorFlag <= #1 1;
                                                frameErrorFlag <= #1 1;
                                        end else if(ackFlags) begin
                                        end else if(ackFlags) begin
                                                frameErrorFlag <= #1 0;
                                                frameErrorFlag <= #1 0;
                                        end
                                        end
                                        nextState <= #1 IDLE_STATE;
                                        nextState <= #1 IDLE_STATE;
                                end else if(ackFlags) begin
                                end else if(ackFlags) begin
                                        frameErrorFlag <= #1 0;
                                        frameErrorFlag <= #1 0;
                                end
                                end
 
                                if(PRECISE_STOP_BIT!=0) begin
 
                                        if(bitClocksCounter==(bitClocksCounterCompare/2)) begin
 
                                                stopBit <= #1 1;
 
                                        end
 
                                end
                        end
                        end
                        default: nextState <= #1 IDLE_STATE;
                        default: nextState <= #1 IDLE_STATE;
                endcase
                endcase
        end
        end
end
end
 
 
endmodule
endmodule
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.