`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: Sebastien Riou
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//
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// Create Date: 23:57:02 09/04/2010
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// Design Name:
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// Module Name: RxCore2
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description: non synthetizable model used as reference in test bench
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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/*
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/*
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module Delay();
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Author: Sebastien Riou (acapola)
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Creation date: 23:57:02 09/04/2010
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task WaitClocks;
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$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
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input [CLOCK_PER_BIT_WIDTH-1:0] limit;
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$LastChangedBy: acapola $
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integer bitClocksCounter;
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$LastChangedRevision: 11 $
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begin
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/RxCoreSpec.v $
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for(bitClocksCounter=0;bitClocksCounter<limit;bitClocksCounter=bitClocksCounter+1) begin
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@(posedge syncClk);
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This file is under the BSD licence:
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end
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Copyright (c) 2011, Sebastien Riou
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end
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endtask
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`default_nettype none
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endmodule
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/*
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non synthetizable model used as reference in test bench
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*/
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*/
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module RxCoreSpec(
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module RxCoreSpec(
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output reg [7:0] dataOut,
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output reg [7:0] dataOut,
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output reg overrunErrorFlag, //new data has been received before dataOut was read
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output reg overrunErrorFlag, //new data has been received before dataOut was read
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output reg dataOutReadyFlag, //new data available
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output reg dataOutReadyFlag, //new data available
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output reg frameErrorFlag, //bad parity or bad stop bits
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output reg frameErrorFlag, //bad parity or bad stop bits
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output reg endOfRx,
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output reg endOfRx,
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output reg run, //rx is definitely started, one of the three flag will be set
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output reg run, //rx is definitely started, one of the three flag will be set
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output reg startBit, //rx is started, but we don't know yet if real rx or just a glitch
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output reg startBit, //rx is started, but we don't know yet if real rx or just a glitch
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input [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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input [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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input stopBit2,//0: 1 stop bit, 1: 2 stop bits
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input stopBit2,//0: 1 stop bit, 1: 2 stop bits
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input ackFlags,
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input ackFlags,
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input serialIn,
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input serialIn,
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input clk,
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input clk,
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input nReset
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input nReset
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);
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);
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parameter CLK_PERIOD = 10;//should be %2
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parameter CLK_PERIOD = 10;//should be %2
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//parameters to override
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//parameters to override
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parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
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parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
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//invert the polarity of the output or not
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//invert the polarity of the output or not
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parameter IN_POLARITY = 1'b0;
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parameter IN_POLARITY = 1'b0;
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parameter PARITY_POLARITY = 1'b0;
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parameter PARITY_POLARITY = 1'b0;
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//default conventions
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//default conventions
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parameter START_BIT = 1'b0;
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parameter START_BIT = 1'b0;
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parameter STOP_BIT1 = 1'b1;
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parameter STOP_BIT1 = 1'b1;
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parameter STOP_BIT2 = 1'b1;
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parameter STOP_BIT2 = 1'b1;
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//constant definition for states
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//constant definition for states
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localparam IDLE_BIT = ~START_BIT;
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localparam IDLE_BIT = ~START_BIT;
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integer bitCounter;
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integer bitCounter;
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reg parityBit;
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reg parityBit;
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reg rxStarted;
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reg rxStarted;
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wire internalIn;
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wire internalIn;
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wire parityError;
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wire parityError;
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assign internalIn = serialIn ^ IN_POLARITY;
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assign internalIn = serialIn ^ IN_POLARITY;
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assign parityError= parityBit ^ internalIn ^ PARITY_POLARITY ^ 1'b1;
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assign parityError= parityBit ^ internalIn ^ PARITY_POLARITY ^ 1'b1;
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reg syncClk;
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reg syncClk;
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/*logic to avoid race condition on flags
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/*logic to avoid race condition on flags
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if internal logic set the flag and at the same time
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if internal logic set the flag and at the same time
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the signal ackFlags is set (that normally clears the flags), the flag should be set
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the signal ackFlags is set (that normally clears the flags), the flag should be set
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*/
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*/
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reg setOverrunErrorFlag;
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reg setOverrunErrorFlag;
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reg nResetOverrunErrorFlag;
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reg nResetOverrunErrorFlag;
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always @(negedge clk) begin
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always @(negedge clk) begin
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setOverrunErrorFlag<=1'b0;
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setOverrunErrorFlag<=1'b0;
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end
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end
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//flag set has priority over flag nReset
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//flag set has priority over flag nReset
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always @(setOverrunErrorFlag,nResetOverrunErrorFlag) begin
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always @(setOverrunErrorFlag,nResetOverrunErrorFlag) begin
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if((setOverrunErrorFlag===1'b1) || (setOverrunErrorFlag===1'bx)) begin
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if((setOverrunErrorFlag===1'b1) || (setOverrunErrorFlag===1'bx)) begin
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overrunErrorFlag<=setOverrunErrorFlag;
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overrunErrorFlag<=setOverrunErrorFlag;
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if(nResetOverrunErrorFlag)
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if(nResetOverrunErrorFlag)
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nResetOverrunErrorFlag=0;
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nResetOverrunErrorFlag=0;
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end else begin
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end else begin
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if(nResetOverrunErrorFlag) begin
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if(nResetOverrunErrorFlag) begin
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overrunErrorFlag<=0;
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overrunErrorFlag<=0;
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nResetOverrunErrorFlag=0;
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nResetOverrunErrorFlag=0;
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end
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end
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end
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end
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end
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end
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reg setDataOutReadyFlag;
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reg setDataOutReadyFlag;
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reg nResetDataOutReadyFlag;
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reg nResetDataOutReadyFlag;
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always @(negedge clk) begin
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always @(negedge clk) begin
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setDataOutReadyFlag<=1'b0;
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setDataOutReadyFlag<=1'b0;
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end
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end
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//flag set has priority over flag nReset
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//flag set has priority over flag nReset
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always @(setDataOutReadyFlag,nResetDataOutReadyFlag) begin
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always @(setDataOutReadyFlag,nResetDataOutReadyFlag) begin
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if((setDataOutReadyFlag===1'b1) || (setDataOutReadyFlag===1'bx)) begin
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if((setDataOutReadyFlag===1'b1) || (setDataOutReadyFlag===1'bx)) begin
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dataOutReadyFlag<=setDataOutReadyFlag;
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dataOutReadyFlag<=setDataOutReadyFlag;
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if(nResetDataOutReadyFlag)
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if(nResetDataOutReadyFlag)
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nResetDataOutReadyFlag=0;
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nResetDataOutReadyFlag=0;
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end else begin
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end else begin
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if(nResetDataOutReadyFlag) begin
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if(nResetDataOutReadyFlag) begin
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dataOutReadyFlag<=0;
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dataOutReadyFlag<=0;
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nResetDataOutReadyFlag=0;
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nResetDataOutReadyFlag=0;
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end
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end
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end
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end
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end
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end
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reg setFrameErrorFlag;
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reg setFrameErrorFlag;
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reg nResetFrameErrorFlag;
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reg nResetFrameErrorFlag;
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always @(negedge clk) begin
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always @(negedge clk) begin
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setFrameErrorFlag<=1'b0;
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setFrameErrorFlag<=1'b0;
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end
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end
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//flag set has priority over flag nReset
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//flag set has priority over flag nReset
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always @(setFrameErrorFlag,nResetFrameErrorFlag) begin
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always @(setFrameErrorFlag,nResetFrameErrorFlag) begin
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if((setFrameErrorFlag===1'b1) || (setFrameErrorFlag===1'bx)) begin
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if((setFrameErrorFlag===1'b1) || (setFrameErrorFlag===1'bx)) begin
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frameErrorFlag<=setFrameErrorFlag;
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frameErrorFlag<=setFrameErrorFlag;
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if(nResetFrameErrorFlag)
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if(nResetFrameErrorFlag)
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nResetFrameErrorFlag=0;
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nResetFrameErrorFlag=0;
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end else begin
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end else begin
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if(nResetFrameErrorFlag) begin
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if(nResetFrameErrorFlag) begin
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frameErrorFlag<=0;
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frameErrorFlag<=0;
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nResetFrameErrorFlag=0;
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nResetFrameErrorFlag=0;
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end
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end
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end
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end
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end
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end
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reg dataOutReadyFlagAckDone;
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reg dataOutReadyFlagAckDone;
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reg frameErrorFlagAckDone;
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reg frameErrorFlagAckDone;
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always @(posedge clk) begin:ACK_FLAGS
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always @(posedge clk) begin:ACK_FLAGS
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if(ackFlags) begin
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if(ackFlags) begin
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if(0==rxStarted)
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if(0==rxStarted)
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nResetOverrunErrorFlag<=1;//otherwise, done in OVERRUN_BIT block
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nResetOverrunErrorFlag<=1;//otherwise, done in OVERRUN_BIT block
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if(dataOutReadyFlag!==1'bx)
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if(dataOutReadyFlag!==1'bx)
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nResetDataOutReadyFlag<=1'b1;
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nResetDataOutReadyFlag<=1'b1;
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dataOutReadyFlagAckDone<=1'b1;
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dataOutReadyFlagAckDone<=1'b1;
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if(frameErrorFlag!==1'bx)
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if(frameErrorFlag!==1'bx)
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nResetFrameErrorFlag<=1'b1;
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nResetFrameErrorFlag<=1'b1;
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frameErrorFlagAckDone<=1'b1;
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frameErrorFlagAckDone<=1'b1;
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end
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end
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end
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end
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reg internalStart;
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reg internalStart;
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integer clockCounter;
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integer clockCounter;
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always@(posedge internalStart) begin:CLOCK_COUNTER
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always@(posedge internalStart) begin:CLOCK_COUNTER
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for(clockCounter=0;clockCounter<(11+stopBit2)*(clocksPerBit+1);clockCounter=clockCounter+1) begin
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for(clockCounter=0;clockCounter<(11+stopBit2)*(clocksPerBit+1);clockCounter=clockCounter+1) begin
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syncClk=0;
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syncClk=0;
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#(CLK_PERIOD/2);
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#(CLK_PERIOD/2);
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syncClk=1;
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syncClk=1;
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#(CLK_PERIOD/2);
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#(CLK_PERIOD/2);
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end
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end
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end
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end
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reg abortStart;
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reg abortStart;
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always@(posedge abortStart) begin:ABORT_START
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always@(posedge abortStart) begin:ABORT_START
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abortStart<=0;
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abortStart<=0;
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startBit<=1'bx;
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startBit<=1'bx;
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#(CLK_PERIOD*(clocksPerBit+1)/4);
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#(CLK_PERIOD*(clocksPerBit+1)/4);
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if(internalIn)
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if(internalIn)
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startBit<=0;
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startBit<=0;
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end
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end
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//Start bit spec
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//Start bit spec
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always@(negedge internalIn) begin:START_BIT_BLK
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always@(negedge internalIn) begin:START_BIT_BLK
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if(frameErrorFlag | overrunErrorFlag) begin
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if(frameErrorFlag | overrunErrorFlag) begin
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//nothing to do, wait clear from outside
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//nothing to do, wait clear from outside
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end else begin
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end else begin
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internalStart<=1;
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internalStart<=1;
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startBit<=1'bx;
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startBit<=1'bx;
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#(CLK_PERIOD*(clocksPerBit+1)/4);
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#(CLK_PERIOD*(clocksPerBit+1)/4);
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internalStart<=0;
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internalStart<=0;
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startBit<=1;
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startBit<=1;
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#(CLK_PERIOD*(clocksPerBit+1)/4);
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#(CLK_PERIOD*(clocksPerBit+1)/4);
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if(internalIn==0) begin
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if(internalIn==0) begin
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startBit<=1'bx;
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startBit<=1'bx;
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#(CLK_PERIOD*(clocksPerBit+1)/4);
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#(CLK_PERIOD*(clocksPerBit+1)/4);
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startBit<=0;
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startBit<=0;
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#(CLK_PERIOD*(clocksPerBit+1)/4);
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#(CLK_PERIOD*(clocksPerBit+1)/4);
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#(CLK_PERIOD*(10+stopBit2)*(clocksPerBit+1));//ignore falling edge until end of the byte
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#(CLK_PERIOD*(10+stopBit2)*(clocksPerBit+1));//ignore falling edge until end of the byte
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end else begin
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end else begin
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abortStart<=1;
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abortStart<=1;
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end
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end
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end
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end
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end
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end
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wire [31:0] stopStart=10*(clocksPerBit+1);
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wire [31:0] stopStart=10*(clocksPerBit+1);
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wire [31:0] stopEnd=((10+stopBit2)*(clocksPerBit+1)+((clocksPerBit+1)*3)/4);
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wire [31:0] stopEnd=((10+stopBit2)*(clocksPerBit+1)+((clocksPerBit+1)*3)/4);
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wire isInStop=(clockCounter>=stopStart) && (clockCounter<stopEnd);
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wire isInStop=(clockCounter>=stopStart) && (clockCounter<stopEnd);
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reg runBitSet;
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reg runBitSet;
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//Run bit spec
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//Run bit spec
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always@(negedge internalIn) begin:RUN_BIT_SET
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always@(negedge internalIn) begin:RUN_BIT_SET
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if(frameErrorFlag | overrunErrorFlag) begin
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if(frameErrorFlag | overrunErrorFlag) begin
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//nothing to do, wait clear from outside
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//nothing to do, wait clear from outside
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end else if(~isInStop) begin
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end else if(~isInStop) begin
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runBitSet<=1'b0;
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runBitSet<=1'b0;
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#(CLK_PERIOD*(clocksPerBit+1)/2);
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#(CLK_PERIOD*(clocksPerBit+1)/2);
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if(internalIn == 0) begin
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if(internalIn == 0) begin
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fork
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fork
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begin
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begin
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runBitSet<=1'b1;
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runBitSet<=1'b1;
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run<=1'bx;
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run<=1'bx;
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#(CLK_PERIOD*(clocksPerBit+1)/4);
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#(CLK_PERIOD*(clocksPerBit+1)/4);
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run<=1;
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run<=1;
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end
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end
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begin
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begin
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#(CLK_PERIOD*(clocksPerBit+1)/2);
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#(CLK_PERIOD*(clocksPerBit+1)/2);
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#(CLK_PERIOD*(9+stopBit2)*(clocksPerBit+1));
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#(CLK_PERIOD*(9+stopBit2)*(clocksPerBit+1));
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end
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end
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join
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join
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end
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end
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end
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end
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end
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end
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always@(posedge runBitSet) begin:RUN_BIT_CLEAR
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always@(posedge runBitSet) begin:RUN_BIT_CLEAR
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#(CLK_PERIOD*(clocksPerBit+1)/2);
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#(CLK_PERIOD*(clocksPerBit+1)/2);
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#(CLK_PERIOD*(((10+stopBit2)*(clocksPerBit+1))-2));
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#(CLK_PERIOD*(((10+stopBit2)*(clocksPerBit+1))-2));
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if(runBitSet)
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if(runBitSet)
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endOfRx<=1'bx;
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endOfRx<=1'bx;
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#(CLK_PERIOD);
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#(CLK_PERIOD);
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if(runBitSet) begin//might be cleared by nReset
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if(runBitSet) begin//might be cleared by nReset
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run<=1'bx;
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run<=1'bx;
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#(CLK_PERIOD*(clocksPerBit+1)/4);
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#(CLK_PERIOD*(clocksPerBit+1)/4);
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endOfRx<=1'b0;
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endOfRx<=1'b0;
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run<=0;
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run<=0;
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end
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end
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end
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end
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//overrun bit spec
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//overrun bit spec
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reg internalOv;
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reg internalOv;
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wire [31:0] minOvCount=(clocksPerBit+1);//WARNING: DATA_OUT block rely on this
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wire [31:0] minOvCount=(clocksPerBit+1);//WARNING: DATA_OUT block rely on this
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wire [31:0] maxOvCount=((clocksPerBit+1)/2)+(clocksPerBit+1)+(clocksPerBit+1)/4;
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wire [31:0] maxOvCount=((clocksPerBit+1)/2)+(clocksPerBit+1)+(clocksPerBit+1)/4;
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always@(posedge syncClk) begin:OVERRUN_BIT
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always@(posedge syncClk) begin:OVERRUN_BIT
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if(clockCounter<maxOvCount) begin//internal requests to set the flag have priority over clear by ackFlags
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if(clockCounter<maxOvCount) begin//internal requests to set the flag have priority over clear by ackFlags
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if(clockCounter==minOvCount)
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if(clockCounter==minOvCount)
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if(dataOutReadyFlag)
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if(dataOutReadyFlag)
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setOverrunErrorFlag <= 1'bx;
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setOverrunErrorFlag <= 1'bx;
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end else if(clockCounter==maxOvCount) begin
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end else if(clockCounter==maxOvCount) begin
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if(1'bx===overrunErrorFlag)
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if(1'bx===overrunErrorFlag)
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setOverrunErrorFlag <= 1;
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setOverrunErrorFlag <= 1;
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end else
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end else
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if(ackFlags)
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if(ackFlags)
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nResetOverrunErrorFlag <= 1;
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nResetOverrunErrorFlag <= 1;
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end
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end
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reg [7:0] dataStorage;
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reg [7:0] dataStorage;
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reg waitStartBit;
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reg waitStartBit;
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//dataOut spec
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//dataOut spec
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//frameErrorFlag spec (1/2)
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//frameErrorFlag spec (1/2)
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always@(negedge internalIn) begin:DATA_OUT
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always@(negedge internalIn) begin:DATA_OUT
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if(frameErrorFlag | overrunErrorFlag) begin
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if(frameErrorFlag | overrunErrorFlag) begin
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//nothing to do, wait clear from outside
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//nothing to do, wait clear from outside
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end else begin
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end else begin
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waitStartBit<=1'b0;
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waitStartBit<=1'b0;
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#(CLK_PERIOD*(clocksPerBit+1)/2);
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#(CLK_PERIOD*(clocksPerBit+1)/2);
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if(internalIn==0) begin
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if(internalIn==0) begin
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#(CLK_PERIOD*(minOvCount-((clocksPerBit+1)/2)));
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#(CLK_PERIOD*(minOvCount-((clocksPerBit+1)/2)));
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fork
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fork
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if(0==dataOutReadyFlag) begin
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if(0==dataOutReadyFlag) begin
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dataOut<=8'bx;
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dataOut<=8'bx;
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#(CLK_PERIOD*(clocksPerBit+1)/2);
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#(CLK_PERIOD*(clocksPerBit+1)/2);
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#(CLK_PERIOD*8*(clocksPerBit+1));//wait 8 bits + parity
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#(CLK_PERIOD*8*(clocksPerBit+1));//wait 8 bits + parity
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parityBit <= ^dataStorage;
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parityBit <= ^dataStorage;
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if(0==(^dataStorage) ^ internalIn ^ PARITY_POLARITY ^ 1'b1) begin
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if(0==(^dataStorage) ^ internalIn ^ PARITY_POLARITY ^ 1'b1) begin
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setDataOutReadyFlag<=1'bx;
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setDataOutReadyFlag<=1'bx;
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dataOutReadyFlagAckDone<=1'b0;
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dataOutReadyFlagAckDone<=1'b0;
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#(CLK_PERIOD*2);//#(CLK_PERIOD*(clocksPerBit+1)/4);//allow 1/4 bit time latency
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#(CLK_PERIOD*2);//#(CLK_PERIOD*(clocksPerBit+1)/4);//allow 1/4 bit time latency
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dataOut<=dataStorage;
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dataOut<=dataStorage;
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if(~dataOutReadyFlagAckDone)
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if(~dataOutReadyFlagAckDone)
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setDataOutReadyFlag<=1'b1;
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setDataOutReadyFlag<=1'b1;
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else
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else
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nResetDataOutReadyFlag<=1'b1;
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nResetDataOutReadyFlag<=1'b1;
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end else begin
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end else begin
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setFrameErrorFlag <= 1'bx;
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setFrameErrorFlag <= 1'bx;
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frameErrorFlagAckDone<=1'b0;
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frameErrorFlagAckDone<=1'b0;
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#(CLK_PERIOD*2);//#(CLK_PERIOD*(clocksPerBit+1)/4);//allow 1/4 bit time latency
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#(CLK_PERIOD*2);//#(CLK_PERIOD*(clocksPerBit+1)/4);//allow 1/4 bit time latency
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if(~frameErrorFlagAckDone)
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if(~frameErrorFlagAckDone)
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setFrameErrorFlag<=1'b1;
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setFrameErrorFlag<=1'b1;
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else
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else
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nResetFrameErrorFlag<=1'b1;
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nResetFrameErrorFlag<=1'b1;
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end
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end
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end
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end
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begin
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begin
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#(CLK_PERIOD*(clocksPerBit+1)/4);//we can detect start bit a 1/4 of bit time before the actual end of the transfer
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#(CLK_PERIOD*(clocksPerBit+1)/4);//we can detect start bit a 1/4 of bit time before the actual end of the transfer
|
#(CLK_PERIOD*(9+stopBit2)*(clocksPerBit+1));
|
#(CLK_PERIOD*(9+stopBit2)*(clocksPerBit+1));
|
#(CLK_PERIOD*(clocksPerBit+1)/2);
|
#(CLK_PERIOD*(clocksPerBit+1)/2);
|
end
|
end
|
join
|
join
|
end
|
end
|
waitStartBit<=1'b1;
|
waitStartBit<=1'b1;
|
end
|
end
|
end
|
end
|
|
|
//frameErrorFlag spec (2/2)
|
//frameErrorFlag spec (2/2)
|
always@(negedge internalIn) begin:FRAME_ERROR
|
always@(negedge internalIn) begin:FRAME_ERROR
|
if(frameErrorFlag | overrunErrorFlag) begin
|
if(frameErrorFlag | overrunErrorFlag) begin
|
//nothing to do, wait clear from outside
|
//nothing to do, wait clear from outside
|
end else begin
|
end else begin
|
if(isInStop) begin
|
if(isInStop) begin
|
setFrameErrorFlag <= 1'bx;
|
setFrameErrorFlag <= 1'bx;
|
frameErrorFlagAckDone<=1'b0;
|
frameErrorFlagAckDone<=1'b0;
|
#(CLK_PERIOD*(clocksPerBit+1)/1);//allow 1 bit time latency
|
#(CLK_PERIOD*(clocksPerBit+1)/1);//allow 1 bit time latency
|
if(~frameErrorFlagAckDone)
|
if(~frameErrorFlagAckDone)
|
setFrameErrorFlag<=1'b1;
|
setFrameErrorFlag<=1'b1;
|
else
|
else
|
nResetFrameErrorFlag<=1'b1;
|
nResetFrameErrorFlag<=1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
initial begin
|
initial begin
|
internalStart=0;
|
internalStart=0;
|
clockCounter=0;
|
clockCounter=0;
|
abortStart=0;
|
abortStart=0;
|
internalOv=0;
|
internalOv=0;
|
end
|
end
|
|
|
always @(negedge internalIn, negedge nReset) begin:MAIN
|
always @(negedge internalIn, negedge nReset) begin:MAIN
|
if(~nReset) begin
|
if(~nReset) begin
|
bitCounter <= 0;
|
bitCounter <= 0;
|
parityBit <= 0;
|
parityBit <= 0;
|
nResetOverrunErrorFlag <= 1'b1;
|
nResetOverrunErrorFlag <= 1'b1;
|
setOverrunErrorFlag <= 1'b0;
|
setOverrunErrorFlag <= 1'b0;
|
nResetDataOutReadyFlag <= 1'b1;
|
nResetDataOutReadyFlag <= 1'b1;
|
setDataOutReadyFlag <= 1'b0;
|
setDataOutReadyFlag <= 1'b0;
|
nResetFrameErrorFlag <= 1'b1;
|
nResetFrameErrorFlag <= 1'b1;
|
setFrameErrorFlag<=1'b0;
|
setFrameErrorFlag<=1'b0;
|
endOfRx<=1'b0;
|
endOfRx<=1'b0;
|
run <= 0;
|
run <= 0;
|
startBit <= 0;
|
startBit <= 0;
|
runBitSet<=0;
|
runBitSet<=0;
|
end else if(frameErrorFlag | overrunErrorFlag) begin
|
end else if(frameErrorFlag | overrunErrorFlag) begin
|
//nothing to do, wait clear from outside
|
//nothing to do, wait clear from outside
|
end else begin
|
end else begin
|
rxStarted<=1'b1;
|
rxStarted<=1'b1;
|
#(CLK_PERIOD*(clocksPerBit+1)/2);
|
#(CLK_PERIOD*(clocksPerBit+1)/2);
|
if(internalIn == 0) begin
|
if(internalIn == 0) begin
|
@(posedge clk);
|
@(posedge clk);
|
for(bitCounter=0;bitCounter<8;bitCounter=bitCounter+1) begin
|
for(bitCounter=0;bitCounter<8;bitCounter=bitCounter+1) begin
|
#(CLK_PERIOD*(clocksPerBit+1)/1);
|
#(CLK_PERIOD*(clocksPerBit+1)/1);
|
if(~dataOutReadyFlag) begin
|
if(~dataOutReadyFlag) begin
|
dataStorage[bitCounter]<=internalIn;
|
dataStorage[bitCounter]<=internalIn;
|
end
|
end
|
end
|
end
|
#(CLK_PERIOD*(clocksPerBit+1)/1);
|
#(CLK_PERIOD*(clocksPerBit+1)/1);
|
#(CLK_PERIOD*(clocksPerBit+1)/1);
|
#(CLK_PERIOD*(clocksPerBit+1)/1);
|
if(stopBit2) begin
|
if(stopBit2) begin
|
#(CLK_PERIOD*(clocksPerBit+1)/1);
|
#(CLK_PERIOD*(clocksPerBit+1)/1);
|
end
|
end
|
rxStarted <= 1'b0;
|
rxStarted <= 1'b0;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
`default_nettype wire
|
|
|
No newline at end of file
|
No newline at end of file
|
