/*
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/*
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Author: Sebastien Riou (acapola)
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Author: Sebastien Riou (acapola)
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Creation date: 21:16:10 08/29/2010
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Creation date: 21:16:10 08/29/2010
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$LastChangedDate: 2011-01-29 17:13:49 +0100 (Sat, 29 Jan 2011) $
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$LastChangedDate: 2011-03-07 14:17:52 +0100 (Mon, 07 Mar 2011) $
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$LastChangedBy: acapola $
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$LastChangedBy: acapola $
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$LastChangedRevision: 12 $
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$LastChangedRevision: 18 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/TxCore.v $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/TxCore.v $
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This file is under the BSD licence:
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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Copyright (c) 2011, Sebastien Riou
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All rights reserved.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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`default_nettype none
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`default_nettype none
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module TxCore
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module TxCore
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#(//parameters to override
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#(//parameters to override
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parameter DIVIDER_WIDTH = 1,
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parameter DIVIDER_WIDTH = 1,
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parameter CLOCK_PER_BIT_WIDTH = 13,//allow to support default speed of ISO7816
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parameter CLOCK_PER_BIT_WIDTH = 13,//allow to support default speed of ISO7816
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//default conventions
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//default conventions
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parameter START_BIT = 1'b0,
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parameter START_BIT = 1'b0,
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parameter STOP_BIT1 = 1'b1
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parameter STOP_BIT1 = 1'b1
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)
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)
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(
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(
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output wire comClk,
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output wire comClk,
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output wire serialOut,
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output wire serialOut,
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output wire run,
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output wire run,
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output reg endOfTx,
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output reg endOfTx,
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output wire full,
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output wire full,
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output wire stopBits, //1 during stop bits
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output wire stopBits, //1 during stop bits
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input wire [7:0] dataIn,
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input wire [7:0] dataIn,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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input wire loadDataIn, //evaluated only when full=0, when full goes to one, dataIn has been read
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input wire loadDataIn, //evaluated only when full=0, when full goes to one, dataIn has been read
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input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
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input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
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input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
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input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
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input wire msbFirst, //if 1, bits will be send in the order startBit, b7, b6, b5...b0, parity
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input wire msbFirst, //if 1, bits will be send in the order startBit, b7, b6, b5...b0, parity
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input wire clk,
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input wire clk,
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input wire nReset
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input wire nReset
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);
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);
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//constant definition for state
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//constant definition for state
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localparam IDLE_STATE = 0;
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localparam IDLE_STATE = 0;
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localparam START_STATE = 1;
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localparam START_STATE = 1;
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localparam SEND_DATA_STATE = 2;
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localparam SEND_DATA_STATE = 2;
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localparam SEND_PARITY_STATE = 3;
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localparam SEND_PARITY_STATE = 3;
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localparam SEND_STOP1_STATE = 4;
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localparam SEND_STOP1_STATE = 4;
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localparam SEND_STOP2_STATE = 5;
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localparam SEND_STOP2_STATE = 5;
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localparam IDLE_BIT = ~START_BIT;
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localparam IDLE_BIT = ~START_BIT;
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localparam STOP_BIT2 = STOP_BIT1;
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localparam STOP_BIT2 = STOP_BIT1;
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wire [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounter;
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wire [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounter;
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wire bitClocksCounterEarlyMatch;
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wire bitClocksCounterEarlyMatch;
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wire bitClocksCounterMatch;
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wire bitClocksCounterMatch;
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reg [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounterCompare;
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reg [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounterCompare;
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reg bitClocksCounterInc;
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reg bitClocksCounterInc;
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reg bitClocksCounterClear;
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reg bitClocksCounterClear;
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wire bitClocksCounterInitVal;
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wire bitClocksCounterInitVal;
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Counter #( .DIVIDER_WIDTH(DIVIDER_WIDTH),
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Counter #( .DIVIDER_WIDTH(DIVIDER_WIDTH),
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.WIDTH(CLOCK_PER_BIT_WIDTH),
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.WIDTH(CLOCK_PER_BIT_WIDTH),
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.WIDTH_INIT(1))
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.WIDTH_INIT(1))
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bitClocksCounterModule(
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bitClocksCounterModule(
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.counter(bitClocksCounter),
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.counter(bitClocksCounter),
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.earlyMatch(bitClocksCounterEarlyMatch),
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.earlyMatch(bitClocksCounterEarlyMatch),
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.match(bitClocksCounterMatch),
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.match(bitClocksCounterMatch),
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.dividedClk(comClk),
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.dividedClk(comClk),
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.divider(clkPerCycle),
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.divider(clkPerCycle),
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.compare(bitClocksCounterCompare),
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.compare(bitClocksCounterCompare),
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.inc(bitClocksCounterInc),
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.inc(bitClocksCounterInc),
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.clear(bitClocksCounterClear),
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.clear(bitClocksCounterClear),
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.initVal(bitClocksCounterInitVal),
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.initVal(bitClocksCounterInitVal),
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.clk(clk),
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.clk(clk),
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.nReset(nReset));
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.nReset(nReset));
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reg [2:0] nextState;
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reg [2:0] nextState;
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reg [2:0] bitCounter;
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reg [2:0] bitCounter;
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reg [7:0] dataBuffer;
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reg [7:0] dataBuffer;
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reg parityBit;
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reg parityBit;
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wire internalOut;
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wire internalOut;
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wire dataBit;
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wire dataBit;
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//after a tx operation, during the first cycle in IDLE_STATE, run bit must be still set
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//after a tx operation, during the first cycle in IDLE_STATE, run bit must be still set
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//(it is entered one cycle before the completion of the operation, so we use bitClocksCounter[0]
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//(it is entered one cycle before the completion of the operation, so we use bitClocksCounter[0]
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//to implement this behavior)
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//to implement this behavior)
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assign run = (nextState == IDLE_STATE) ? bitClocksCounter[0] : 1'b1;
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assign run = (nextState == IDLE_STATE) ? bitClocksCounter[0] : 1'b1;
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assign full = (nextState != IDLE_STATE);
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assign full = (nextState != IDLE_STATE);
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assign stopBits = (nextState == SEND_STOP1_STATE)|(nextState == SEND_STOP2_STATE)|((nextState == IDLE_STATE) & bitClocksCounter[0]);
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assign stopBits = (nextState == SEND_STOP1_STATE)|(nextState == SEND_STOP2_STATE)|((nextState == IDLE_STATE) & bitClocksCounter[0]);
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assign serialOut = internalOut;
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assign serialOut = internalOut;
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wire [2:0] bitIndex = msbFirst ? 7-bitCounter : bitCounter;
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wire [2:0] bitIndex = msbFirst ? 7-bitCounter : bitCounter;
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assign dataBit = dataBuffer[bitIndex];
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assign dataBit = dataBuffer[bitIndex];
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wire [0:5] bitSel;
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wire [0:5] bitSel;
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assign bitSel = {IDLE_BIT, START_BIT, dataBit, parityBit, STOP_BIT1, STOP_BIT2};
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assign bitSel = {IDLE_BIT, START_BIT, dataBit, parityBit, STOP_BIT1, STOP_BIT2};
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assign internalOut = bitSel[nextState];
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assign internalOut = bitSel[nextState];
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assign bitClocksCounterInitVal=0;
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assign bitClocksCounterInitVal=0;
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always @(nextState) begin
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always @(*) begin
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case(nextState)
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case(nextState)
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START_STATE:
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START_STATE:
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assign bitClocksCounterCompare = clocksPerBit-1;
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bitClocksCounterCompare = clocksPerBit-1'b1;
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SEND_STOP2_STATE:
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SEND_STOP2_STATE:
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assign bitClocksCounterCompare = clocksPerBit-1;
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bitClocksCounterCompare = clocksPerBit-1'b1;
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default:
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default:
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assign bitClocksCounterCompare = clocksPerBit;
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bitClocksCounterCompare = clocksPerBit;
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endcase
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endcase
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end
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end
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always @(nextState) begin
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always @(nextState) begin
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case(nextState)
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case(nextState)
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IDLE_STATE: begin
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IDLE_STATE: begin
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bitClocksCounterInc = 0;
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bitClocksCounterInc = 0;
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bitClocksCounterClear = 1;
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bitClocksCounterClear = 1;
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end
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end
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default: begin
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default: begin
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bitClocksCounterInc = 1;
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bitClocksCounterInc = 1;
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bitClocksCounterClear = 0;
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bitClocksCounterClear = 0;
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end
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end
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endcase
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endcase
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end
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end
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always @(posedge clk, negedge nReset) begin
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always @(posedge clk, negedge nReset) begin
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if(~nReset) begin
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if(~nReset) begin
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nextState <= #1 IDLE_STATE;
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nextState <= #1 IDLE_STATE;
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bitCounter <= #1 0;
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bitCounter <= #1 0;
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endOfTx <= #1 1'b0;
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endOfTx <= #1 1'b0;
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end else begin
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end else begin
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case(nextState)
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case(nextState)
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IDLE_STATE: begin
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IDLE_STATE: begin
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if(loadDataIn) begin
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if(loadDataIn) begin
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dataBuffer <= #1 dataIn;
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dataBuffer <= #1 dataIn;
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parityBit <= #1 oddParity;
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parityBit <= #1 oddParity;
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nextState <= #1 START_STATE;
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nextState <= #1 START_STATE;
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end
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end
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end
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end
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START_STATE: begin
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START_STATE: begin
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if(bitClocksCounterMatch) begin
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if(bitClocksCounterMatch) begin
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nextState <= #1 SEND_DATA_STATE;
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nextState <= #1 SEND_DATA_STATE;
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end
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end
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end
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end
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SEND_DATA_STATE: begin
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SEND_DATA_STATE: begin
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if(bitClocksCounterMatch) begin
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if(bitClocksCounterMatch) begin
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bitCounter <= #1 (bitCounter + 1'b1) & 3'b111;
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bitCounter <= #1 (bitCounter + 1'b1) & 3'b111;
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parityBit <= #1 parityBit ^ dataBit;
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parityBit <= #1 parityBit ^ dataBit;
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if(bitCounter == 7)
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if(bitCounter == 7)
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nextState <= #1 SEND_PARITY_STATE;
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nextState <= #1 SEND_PARITY_STATE;
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end
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end
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end
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end
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SEND_PARITY_STATE: begin
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SEND_PARITY_STATE: begin
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if(bitClocksCounterMatch) begin
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if(bitClocksCounterMatch) begin
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if(stopBit2)
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if(stopBit2)
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nextState <= #1 SEND_STOP1_STATE;
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nextState <= #1 SEND_STOP1_STATE;
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else
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else
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nextState <= #1 SEND_STOP2_STATE;//if single stop bit, we skip STOP1 state
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nextState <= #1 SEND_STOP2_STATE;//if single stop bit, we skip STOP1 state
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end
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end
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end
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end
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SEND_STOP1_STATE: begin
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SEND_STOP1_STATE: begin
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if(bitClocksCounterMatch)
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if(bitClocksCounterMatch)
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nextState <= #1 SEND_STOP2_STATE;
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nextState <= #1 SEND_STOP2_STATE;
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end
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end
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SEND_STOP2_STATE: begin
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SEND_STOP2_STATE: begin
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if(bitClocksCounterEarlyMatch)
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if(bitClocksCounterEarlyMatch)
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endOfTx <= #1 1'b1;
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endOfTx <= #1 1'b1;
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if(bitClocksCounterMatch) begin
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if(bitClocksCounterMatch) begin
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nextState <= #1 IDLE_STATE;
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nextState <= #1 IDLE_STATE;
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endOfTx <= #1 1'b0;
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endOfTx <= #1 1'b0;
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end
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end
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end
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end
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default: nextState <= #1 IDLE_STATE;
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default: nextState <= #1 IDLE_STATE;
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endcase
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endcase
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end
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end
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end
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end
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endmodule
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endmodule
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`default_nettype wire
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`default_nettype wire
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