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/*
/*
Author: Sebastien Riou (acapola)
Author: Sebastien Riou (acapola)
Creation date: 23:57:02 08/31/2010
Creation date: 23:57:02 08/31/2010
 
 
$LastChangedDate: 2011-01-29 17:13:49 +0100 (Sat, 29 Jan 2011) $
$LastChangedDate: 2011-02-13 16:20:10 +0100 (Sun, 13 Feb 2011) $
$LastChangedBy: acapola $
$LastChangedBy: acapola $
$LastChangedRevision: 12 $
$LastChangedRevision: 15 $
$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/Uart.v $
$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/Uart.v $
 
 
This file is under the BSD licence:
This file is under the BSD licence:
Copyright (c) 2011, Sebastien Riou
Copyright (c) 2011, Sebastien Riou
 
 
All rights reserved.
All rights reserved.
 
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
 
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
*/
`default_nettype none
`default_nettype none
`timescale 1ns / 1ps
`timescale 1ns / 1ps
 
 
/*
/*
Half duplex UART with 1 byte buffer
Half duplex UART with 1 byte buffer
*/
*/
module BasicHalfDuplexUart
module BasicHalfDuplexUart
#(//parameters to override
#(//parameters to override
        parameter DIVIDER_WIDTH = 1,
        parameter DIVIDER_WIDTH = 1,
        parameter CLOCK_PER_BIT_WIDTH = 13,     //allow to support default speed of ISO7816
        parameter CLOCK_PER_BIT_WIDTH = 13,     //allow to support default speed of ISO7816
        //invert the polarity of the output or not
        //invert the polarity of the output or not
        parameter IN_POLARITY = 1'b0,
        parameter IN_POLARITY = 1'b0,
        parameter PARITY_POLARITY = 1'b1,
        parameter PARITY_POLARITY = 1'b1,
        //default conventions
        //default conventions
        parameter START_BIT = 1'b0,
        parameter START_BIT = 1'b0,
        parameter STOP_BIT1 = 1'b1,
        parameter STOP_BIT1 = 1'b1,
        parameter STOP_BIT2 = 1'b1
        parameter STOP_BIT2 = 1'b1
)
)
(
(
    output wire [7:0] rxData,
    output wire [7:0] rxData,
    output wire overrunErrorFlag,       //new data has been received before dataOut was read
    output wire overrunErrorFlag,       //new data has been received before dataOut was read
    output wire dataOutReadyFlag,       //new data available
    output wire dataOutReadyFlag,       //new data available
    output wire frameErrorFlag,         //bad parity or bad stop bits
    output wire frameErrorFlag,         //bad parity or bad stop bits
    output wire txRun,                                  //tx is started
    output wire txRun,                                  //tx is started
    output wire endOfRx,           //one cycle pulse: 1 during last cycle of last stop bit of rx
    output wire endOfRx,           //one cycle pulse: 1 during last cycle of last stop bit of rx
    output wire rxRun,                                  //rx is definitely started, one of the three flag will be set
    output wire rxRun,                                  //rx is definitely started, one of the three flag will be set
    output wire rxStartBit,                     //rx is started, but we don't know yet if real rx or just a glitch
    output wire rxStartBit,                     //rx is started, but we don't know yet if real rx or just a glitch
    output wire txFull,
    output wire txFull,
    output wire isTx,              //1 only when tx is ongoing. Indicates the direction of the com line.
    output wire isTx,              //1 only when tx is ongoing. Indicates the direction of the com line.
    output wire endOfTx,           //one cycle pulse: 1 during last cycle of last stop bit of tx
    output wire endOfTx,           //one cycle pulse: 1 during last cycle of last stop bit of tx
 
 
         input wire serialIn,                           //signals to merged into a inout signal according to "isTx"
         input wire serialIn,                           //signals to merged into a inout signal according to "isTx"
         output wire serialOut,
         output wire serialOut,
         output wire comClk,
         output wire comClk,
 
 
    input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
    input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
         input wire [7:0] txData,
         input wire [7:0] txData,
         input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
         input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
         input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
         input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
         input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
         input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
    input wire msbFirst,  //if 1, bits order is: startBit, b7, b6, b5...b0, parity
    input wire msbFirst,  //if 1, bits order is: startBit, b7, b6, b5...b0, parity
         input wire startTx,
         input wire startTx,
         input wire ackFlags,
         input wire ackFlags,
         input wire clk,
         input wire clk,
    input wire nReset
    input wire nReset
    );
    );
 
 
wire rxSerialIn = isTx ? STOP_BIT1 : serialIn;
wire rxSerialIn = isTx ? STOP_BIT1 : serialIn;
wire loadDataIn;
wire loadDataIn;
wire txStopBits;
wire txStopBits;
assign isTx = txRun & ~txStopBits;
assign isTx = txRun & ~txStopBits;
assign loadDataIn = startTx & ~rxStartBit & (~rxRun | endOfRx);
assign loadDataIn = startTx & ~rxStartBit & (~rxRun | endOfRx);
 
 
reg [CLOCK_PER_BIT_WIDTH-1:0] safeClocksPerBit;
reg [CLOCK_PER_BIT_WIDTH-1:0] safeClocksPerBit;
 
reg safeStopBit2;
 
reg safeOddParity;
 
reg safeMsbFirst;
always @(posedge clk, negedge nReset) begin
always @(posedge clk, negedge nReset) begin
        if(~nReset) begin
        if(~nReset) begin
                safeClocksPerBit<=clocksPerBit;
                safeClocksPerBit<=clocksPerBit;
 
                safeStopBit2<=stopBit2;
 
                safeOddParity<=oddParity;
 
                safeMsbFirst<=msbFirst;
        end else if(endOfRx|endOfTx|~(rxRun|rxStartBit|txRun)) begin
        end else if(endOfRx|endOfTx|~(rxRun|rxStartBit|txRun)) begin
                safeClocksPerBit<=clocksPerBit;
                safeClocksPerBit<=clocksPerBit;
 
                safeStopBit2<=stopBit2;
 
                safeOddParity<=oddParity;
 
                safeMsbFirst<=msbFirst;
        end
        end
end
end
 
 
wire stopBit;
wire stopBit;
// Instantiate the module
// Instantiate the module
RxCoreSelfContained #(
RxCoreSelfContained #(
                .DIVIDER_WIDTH(DIVIDER_WIDTH),
                .DIVIDER_WIDTH(DIVIDER_WIDTH),
                .CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH)
                .CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH)
                )
                )
        rxCore (
        rxCore (
    .dataOut(rxData),
    .dataOut(rxData),
    .overrunErrorFlag(overrunErrorFlag),
    .overrunErrorFlag(overrunErrorFlag),
    .dataOutReadyFlag(dataOutReadyFlag),
    .dataOutReadyFlag(dataOutReadyFlag),
    .frameErrorFlag(frameErrorFlag),
    .frameErrorFlag(frameErrorFlag),
    .endOfRx(endOfRx),
    .endOfRx(endOfRx),
    .run(rxRun),
    .run(rxRun),
    .startBit(rxStartBit),
    .startBit(rxStartBit),
         .stopBit(stopBit),
         .stopBit(stopBit),
    .clkPerCycle(clkPerCycle),
    .clkPerCycle(clkPerCycle),
    .clocksPerBit(safeClocksPerBit),
    .clocksPerBit(safeClocksPerBit),
    .stopBit2(stopBit2),
    .stopBit2(safeStopBit2),
    .oddParity(oddParity),
    .oddParity(safeOddParity),
    .msbFirst(msbFirst),
    .msbFirst(safeMsbFirst),
         .ackFlags(ackFlags),
         .ackFlags(ackFlags),
    .serialIn(rxSerialIn),
    .serialIn(rxSerialIn),
    .comClk(comClk),
    .comClk(comClk),
    .clk(clk),
    .clk(clk),
    .nReset(nReset)
    .nReset(nReset)
    );
    );
TxCore #(.DIVIDER_WIDTH(DIVIDER_WIDTH),
TxCore #(.DIVIDER_WIDTH(DIVIDER_WIDTH),
                        .CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH)
                        .CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH)
                )
                )
        txCore (
        txCore (
        .serialOut(serialOut),
        .serialOut(serialOut),
        .run(txRun),
        .run(txRun),
        .endOfTx(endOfTx),
        .endOfTx(endOfTx),
        .full(txFull),
        .full(txFull),
   .stopBits(txStopBits),
   .stopBits(txStopBits),
        .dataIn(txData),
        .dataIn(txData),
        .clkPerCycle(clkPerCycle),
        .clkPerCycle(clkPerCycle),
        .clocksPerBit(safeClocksPerBit),
        .clocksPerBit(safeClocksPerBit),
        .stopBit2(stopBit2),
        .stopBit2(safeStopBit2),
   .oddParity(oddParity),
   .oddParity(safeOddParity),
   .msbFirst(msbFirst),
   .msbFirst(safeMsbFirst),
        .loadDataIn(loadDataIn),
        .loadDataIn(loadDataIn),
        .comClk(comClk),
        .comClk(comClk),
   .clk(clk),
   .clk(clk),
   .nReset(nReset)
   .nReset(nReset)
);
);
 
 
endmodule
endmodule
`default_nettype wire
`default_nettype wire
 
 

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