`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`default_nettype none
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer: Sebastien Riou
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// Engineer: Sebastien Riou
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//
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//
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// Create Date: 23:57:02 08/31/2010
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// Create Date: 23:57:02 08/31/2010
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// Design Name:
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// Design Name:
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// Module Name: Uart
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// Module Name: Uart
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description: Half duplex UART with 1 byte buffer
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// Description: Half duplex UART with 1 byte buffer
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module BasicHalfDuplexUart(
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module BasicHalfDuplexUart(
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output wire [7:0] rxData,
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output wire [7:0] rxData,
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output wire overrunErrorFlag, //new data has been received before dataOut was read
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output wire overrunErrorFlag, //new data has been received before dataOut was read
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output wire dataOutReadyFlag, //new data available
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output wire dataOutReadyFlag, //new data available
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output wire frameErrorFlag, //bad parity or bad stop bits
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output wire frameErrorFlag, //bad parity or bad stop bits
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output wire txRun, //tx is started
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output wire txRun, //tx is started
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output wire endOfRx, //one cycle pulse: 1 during last cycle of last stop bit of rx
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output wire endOfRx, //one cycle pulse: 1 during last cycle of last stop bit of rx
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output wire rxRun, //rx is definitely started, one of the three flag will be set
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output wire rxRun, //rx is definitely started, one of the three flag will be set
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output wire rxStartBit, //rx is started, but we don't know yet if real rx or just a glitch
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output wire rxStartBit, //rx is started, but we don't know yet if real rx or just a glitch
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output wire txFull,
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output wire txFull,
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output wire isTx, //1 only when tx is ongoing. Indicates the direction of the com line.
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output wire isTx, //1 only when tx is ongoing. Indicates the direction of the com line.
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input wire serialIn, //signals to merged into a inout signal according to "isTx"
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input wire serialIn, //signals to merged into a inout signal according to "isTx"
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output wire serialOut,
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output wire serialOut,
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output wire comClk,
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output wire comClk,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire [7:0] txData,
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input wire [7:0] txData,
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input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
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input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
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input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
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input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
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input wire msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
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input wire msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
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input wire startTx,
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input wire startTx,
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input wire ackFlags,
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input wire ackFlags,
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input wire clk,
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input wire clk,
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input wire nReset
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input wire nReset
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);
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);
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//parameters to override
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//parameters to override
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parameter DIVIDER_WIDTH = 1;
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parameter DIVIDER_WIDTH = 1;
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parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
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parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
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//invert the polarity of the output or not
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//invert the polarity of the output or not
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parameter IN_POLARITY = 1'b0;
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parameter IN_POLARITY = 1'b0;
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parameter PARITY_POLARITY = 1'b1;
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parameter PARITY_POLARITY = 1'b1;
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//default conventions
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//default conventions
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parameter START_BIT = 1'b0;
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parameter START_BIT = 1'b0;
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parameter STOP_BIT1 = 1'b1;
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parameter STOP_BIT1 = 1'b1;
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parameter STOP_BIT2 = 1'b1;
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parameter STOP_BIT2 = 1'b1;
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//constant definition for states
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//constant definition for states
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localparam IDLE_STATE = 3'b000;
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localparam IDLE_STATE = 3'b000;
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localparam RX_STATE = 3'b001;
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localparam RX_STATE = 3'b001;
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localparam TX_STATE = 3'b011;
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localparam TX_STATE = 3'b011;
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wire rxSerialIn = isTx ? STOP_BIT1 : serialIn;
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wire rxSerialIn = isTx ? STOP_BIT1 : serialIn;
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//wire serialOut;
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//wire serialOut;
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wire loadDataIn;
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wire loadDataIn;
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wire txStopBits;
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wire txStopBits;
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assign isTx = txRun & ~txStopBits;
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assign isTx = txRun & ~txStopBits;
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//let this to top level to avoid inout signal
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//let this to top level to avoid inout signal
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//assign serialLine = isTx ? serialOut : 1'bz;
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//assign serialLine = isTx ? serialOut : 1'bz;
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assign loadDataIn = startTx & ~rxStartBit & (~rxRun | endOfRx);
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assign loadDataIn = startTx & ~rxStartBit & (~rxRun | endOfRx);
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/*//complicated approach... instead we can simply divide the clock at lower levels
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/*//complicated approach... instead we can simply divide the clock at lower levels
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wire useEarlyComClk = |clkPerCycle ? 1'b1:1'b0;
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wire useEarlyComClk = |clkPerCycle ? 1'b1:1'b0;
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reg dividedClk;
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reg dividedClk;
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wire earlyComClk;//earlier than comClk by 1 cycle of clk (use to make 1 cycle pulse signals)
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wire earlyComClk;//earlier than comClk by 1 cycle of clk (use to make 1 cycle pulse signals)
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always @(posedge clk)begin
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always @(posedge clk)begin
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if(useEarlyComClk)
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if(useEarlyComClk)
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dividedClk <= earlyComClk;
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dividedClk <= earlyComClk;
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end
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end
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assign comClk=useEarlyComClk ? dividedClk : clk;//clock for communication
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assign comClk=useEarlyComClk ? dividedClk : clk;//clock for communication
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wire endOfRxComClk;//pulse of 1 cycle of comClk
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wire endOfRxComClk;//pulse of 1 cycle of comClk
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assign endOfRx = useEarlyComClk ? endOfRxComClk & earlyComClk & ~comClk : endOfRxComClk;//pulse of 1 cycle of clk
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assign endOfRx = useEarlyComClk ? endOfRxComClk & earlyComClk & ~comClk : endOfRxComClk;//pulse of 1 cycle of clk
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ClkDivider #(.DIVIDER_WIDTH(DIVIDER_WIDTH))
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ClkDivider #(.DIVIDER_WIDTH(DIVIDER_WIDTH))
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clkDivider(
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clkDivider(
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.nReset(nReset),
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.nReset(nReset),
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.clk(clk),
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.clk(clk),
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.divider(clkPerCycle),
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.divider(clkPerCycle),
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.dividedClk(earlyComClk)
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.dividedClk(earlyComClk)
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);
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);
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*/
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*/
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wire stopBit;
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// Instantiate the module
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// Instantiate the module
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RxCoreSelfContained #(
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RxCoreSelfContained #(
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.DIVIDER_WIDTH(DIVIDER_WIDTH),
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.DIVIDER_WIDTH(DIVIDER_WIDTH))
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.PARITY_POLARITY(PARITY_POLARITY))
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rxCore (
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rxCore (
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.dataOut(rxData),
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.dataOut(rxData),
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.overrunErrorFlag(overrunErrorFlag),
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.overrunErrorFlag(overrunErrorFlag),
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.dataOutReadyFlag(dataOutReadyFlag),
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.dataOutReadyFlag(dataOutReadyFlag),
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.frameErrorFlag(frameErrorFlag),
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.frameErrorFlag(frameErrorFlag),
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.endOfRx(endOfRx),
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.endOfRx(endOfRx),
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.run(rxRun),
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.run(rxRun),
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.startBit(rxStartBit),
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.startBit(rxStartBit),
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.stopBit(stopBit),
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.clkPerCycle(clkPerCycle),
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.clkPerCycle(clkPerCycle),
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.clocksPerBit(clocksPerBit),
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.clocksPerBit(clocksPerBit),
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.stopBit2(stopBit2),
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.stopBit2(stopBit2),
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.oddParity(oddParity),
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.oddParity(oddParity),
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.msbFirst(msbFirst),
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.msbFirst(msbFirst),
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.ackFlags(ackFlags),
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.ackFlags(ackFlags),
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.serialIn(rxSerialIn),
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.serialIn(rxSerialIn),
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.comClk(comClk),
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.comClk(comClk),
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.clk(clk),
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.clk(clk),
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.nReset(nReset)
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.nReset(nReset)
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);
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);
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TxCore #(.DIVIDER_WIDTH(DIVIDER_WIDTH))
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TxCore #(.DIVIDER_WIDTH(DIVIDER_WIDTH))
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txCore (
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txCore (
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.serialOut(serialOut),
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.serialOut(serialOut),
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.run(txRun),
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.run(txRun),
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.full(txFull),
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.full(txFull),
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.stopBits(txStopBits),
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.stopBits(txStopBits),
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.dataIn(txData),
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.dataIn(txData),
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.clkPerCycle(clkPerCycle),
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.clkPerCycle(clkPerCycle),
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.clocksPerBit(clocksPerBit),
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.clocksPerBit(clocksPerBit),
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.stopBit2(stopBit2),
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.stopBit2(stopBit2),
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.oddParity(oddParity),
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.oddParity(oddParity),
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.msbFirst(msbFirst),
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.msbFirst(msbFirst),
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.loadDataIn(loadDataIn),
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.loadDataIn(loadDataIn),
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.comClk(comClk),
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.comClk(comClk),
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.clk(clk),
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.clk(clk),
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.nReset(nReset)
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.nReset(nReset)
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);
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);
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endmodule
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endmodule
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