/*
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/*
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Author: Sebastien Riou (acapola)
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Author: Sebastien Riou (acapola)
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Creation date: 22:22:43 01/10/2011
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Creation date: 22:22:43 01/10/2011
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$LastChangedDate: 2011-02-09 13:34:14 +0100 (Wed, 09 Feb 2011) $
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$LastChangedDate: 2011-02-10 16:40:57 +0100 (Thu, 10 Feb 2011) $
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$LastChangedBy: acapola $
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$LastChangedBy: acapola $
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$LastChangedRevision: 13 $
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$LastChangedRevision: 14 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/DummyCard.v $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/DummyCard.v $
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This file is under the BSD licence:
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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Copyright (c) 2011, Sebastien Riou
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All rights reserved.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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`default_nettype none
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`default_nettype none
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module DummyCard(
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module DummyCard(
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input wire isoReset,
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input wire isoReset,
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input wire isoClk,
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input wire isoClk,
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input wire isoVdd,
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input wire isoVdd,
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inout wire isoSio
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inout wire isoSio
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);
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);
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// Inputs
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// Inputs
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wire [0:0] clkPerCycle=0;
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wire [0:0] clkPerCycle=0;
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reg [7:0] dataIn;
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reg [7:0] dataIn;
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reg nWeDataIn;
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reg nWeDataIn;
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reg nCsDataOut;
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reg nCsDataOut;
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reg nCsStatusOut;
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reg nCsStatusOut;
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// Outputs
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// Outputs
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wire [7:0] dataOut;
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wire [7:0] dataOut;
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wire [7:0] statusOut;
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wire [7:0] statusOut;
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wire serialOut;
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wire serialOut;
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reg [12:0] cyclesPerEtu;
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reg [12:0] cyclesPerEtu;
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wire cardIsoClk;//card use its own generated clock (like true UARTs)
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wire cardIsoClk;//card use its own generated clock (like true UARTs)
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HalfDuplexUartIf uartIf (
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HalfDuplexUartIf uartIf (
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.nReset(isoReset),
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.nReset(isoReset),
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.clk(isoClk),
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.clk(isoClk),
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.clkPerCycle(clkPerCycle),
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.clkPerCycle(clkPerCycle),
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.dataIn(dataIn),
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.dataIn(dataIn),
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.nWeDataIn(nWeDataIn),
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.nWeDataIn(nWeDataIn),
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.clocksPerBit(cyclesPerEtu),
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.clocksPerBit(cyclesPerEtu),
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.dataOut(dataOut),
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.dataOut(dataOut),
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.nCsDataOut(nCsDataOut),
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.nCsDataOut(nCsDataOut),
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.statusOut(statusOut),
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.statusOut(statusOut),
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.nCsStatusOut(nCsStatusOut),
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.nCsStatusOut(nCsStatusOut),
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.serialIn(isoSio),
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.serialIn(isoSio),
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.serialOut(serialOut),
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.serialOut(serialOut),
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.comClk(cardIsoClk)
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.comClk(cardIsoClk)
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);
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);
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reg sendAtr;
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reg sendAtr;
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reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
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reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
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reg [7:0] buffer[256+5:0];
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reg [7:0] buffer[256+5:0];
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localparam CLA_I= 8*4;
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localparam CLA_I= 8*4;
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localparam INS_I= 8*3;
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localparam INS_I= 8*3;
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localparam P1_I = 8*2;
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localparam P1_I = 8*2;
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localparam P2_I = 8*1;
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localparam P2_I = 8*1;
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localparam P3_I = 0;
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localparam P3_I = 0;
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reg [CLA_I+7:0] tpduHeader;
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reg [CLA_I+7:0] tpduHeader;
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wire COM_statusOut=statusOut;
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wire COM_statusOut=statusOut;
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wire COM_clk=isoClk;
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wire COM_clk=isoClk;
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integer COM_errorCnt;
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integer COM_errorCnt;
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wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
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wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
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assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
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assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
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`include "ComDriverTasks.v"
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`include "ComDriverTasks.v"
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assign isoSio = isTx ? serialOut : 1'bz;
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assign isoSio = isTx ? serialOut : 1'bz;
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/*T=0 card model
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/*T=0 card model
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ATR:
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ATR:
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3B/3F 94 97 80 1F 42 BA BE BA BE
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3B/3F 94 97 80 1F 42 BA BE BA BE
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3B 9E 96 80 1F C7 80 31 E0 73 FE 21 1B 66 D0 00 28 24 01 00 0D
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Implemented commands:
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Implemented commands:
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write buffer:
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write buffer:
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tpdu: 00 0C 00 00 LC data
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tpdu: 00 0C 00 00 LC data
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sw: 90 00
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sw: 90 00
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read buffer:
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read buffer:
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tpdu: 00 0A 00 00 LE
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tpdu: 00 0A 00 00 LE
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response: data
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response: data
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sw: 90 00
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sw: 90 00
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any other:
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any other:
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sw: 69 86
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sw: 69 86
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*/
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*/
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task sendAckByte;
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task sendAckByte;
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sendByte(tpduHeader[INS_I+7:INS_I]);
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sendByte(tpduHeader[INS_I+7:INS_I]);
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endtask
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endtask
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task writeBufferCmd;
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task writeBufferCmd;
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integer i;
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integer i;
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begin
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begin
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sendAckByte;
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sendAckByte;
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for(i=0;i<tpduHeader[P3_I+7:P3_I];i=i+1) begin
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for(i=0;i<tpduHeader[P3_I+7:P3_I];i=i+1) begin
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receiveByte(buffer[i]);
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receiveByte(buffer[i]);
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end
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end
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sendHexBytes("9000");//sendWord(16'h9000);
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sendHexBytes("9000");//sendWord(16'h9000);
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end
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end
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endtask
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endtask
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task readBufferCmd;
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task readBufferCmd;
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integer i;
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integer i;
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integer le;
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integer le;
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begin
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begin
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sendAckByte;
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sendAckByte;
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le=tpduHeader[P3_I+7:P3_I];
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le=tpduHeader[P3_I+7:P3_I];
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if(0==le) le=256;
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if(0==le) le=256;
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for(i=0;i<le;i=i+1) begin
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for(i=0;i<le;i=i+1) begin
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sendByte(buffer[i]);
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sendByte(buffer[i]);
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end
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end
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sendHexBytes("9000");//sendWord(16'h9000);
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sendHexBytes("9000");//sendWord(16'h9000);
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end
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end
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endtask
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endtask
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integer i;
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integer i;
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always @(posedge isoClk, negedge isoReset) begin
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always @(posedge isoClk, negedge isoReset) begin
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if(~isoReset) begin
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if(~isoReset) begin
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nWeDataIn<=1'b1;
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nWeDataIn<=1'b1;
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nCsDataOut<=1'b1;
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nCsDataOut<=1'b1;
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nCsStatusOut<=1'b1;
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nCsStatusOut<=1'b1;
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tsCnt<=9'b0;
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tsCnt<=9'b0;
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sendAtr<=1'b1;
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sendAtr<=1'b1;
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cyclesPerEtu <= 13'd372-1'b1;
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cyclesPerEtu <= 13'd372-1'b1;
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end else if(tsCnt!=9'd400) begin
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end else if(tsCnt!=9'd400) begin
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tsCnt <= tsCnt + 1'b1;
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tsCnt <= tsCnt + 1'b1;
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end else if(sendAtr) begin
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end else if(sendAtr) begin
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sendAtr<=1'b0;
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sendAtr<=1'b0;
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//sendHexBytes("3B00");
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//sendHexBytes("3B00");
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sendHexBytes("3B");
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sendHexBytes("3B");
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//sendHexBytes("3F");
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//sendHexBytes("3F");
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sendHexBytes("9497801F42BABEBABE");
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//sendHexBytes("9497801F42BABEBABE");
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//sendHexBytes("9E 97 80 1F C7 80 31 E0 73 FE 21 1B 66 D0 00 28 24 01 00 0D");
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sendHexBytes("9E 97 80 1F C7 80 31 E0 73 FE 21 1B 66 D0 00 28 24 01 00 ");
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waitEndOfTx;
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waitEndOfTx;
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end else begin
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end else begin
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//get CLA
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//get CLA
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receiveByte(tpduHeader[CLA_I+:8]);
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receiveByte(tpduHeader[CLA_I+:8]);
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//get INS~P2 or PPS
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//get INS~P2 or PPS
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for(i=1;i<4;i=i+1)
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for(i=1;i<4;i=i+1)
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receiveByte(tpduHeader[(CLA_I-(i*8))+:8]);
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receiveByte(tpduHeader[(CLA_I-(i*8))+:8]);
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if(8'hFF==tpduHeader[CLA_I+:8]) begin
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if(8'hFF==tpduHeader[CLA_I+:8]) begin
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//support only PPS8 for the time being
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//support only PPS8 for the time being
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if(32'hFF109778==tpduHeader[7+CLA_I:P2_I]) begin
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if(32'hFF109778==tpduHeader[7+CLA_I:P2_I]) begin
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sendHexBytes("FF109778");
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sendHexBytes("FF109778");
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waitEndOfTx;
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waitEndOfTx;
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cyclesPerEtu <= 13'd8-1'b1;
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cyclesPerEtu <= 13'd8-1'b1;
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end
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end
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end else begin
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end else begin
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//tpdu: get P3
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//tpdu: get P3
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receiveByte(tpduHeader[P3_I+:8]);
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receiveByte(tpduHeader[P3_I+:8]);
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//dispatch
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//dispatch
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case(tpduHeader[7+CLA_I:P2_I])
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case(tpduHeader[7+CLA_I:P2_I])
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32'h000C0000: writeBufferCmd;
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32'h000C0000: writeBufferCmd;
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32'h000A0000: readBufferCmd;
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32'h000A0000: readBufferCmd;
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default: sendHexBytes("6986");//sendWord(16'h6986);
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default: sendHexBytes("6986");//sendWord(16'h6986);
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endcase
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endcase
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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`default_nettype wire
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`default_nettype wire
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