`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`default_nettype none
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`default_nettype none
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 22:22:43 01/10/2011
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// Create Date: 22:22:43 01/10/2011
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// Design Name: HalfDuplexUartIf
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// Design Name: HalfDuplexUartIf
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// Module Name: dummyCard.v
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// Module Name: dummyCard.v
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// Project Name: Uart
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// Project Name: Uart
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// Target Device:
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// Target Device:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Verilog Test Fixture created by ISE for module: HalfDuplexUartIf
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// Verilog Test Fixture created by ISE for module: HalfDuplexUartIf
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module DummyCard(
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module DummyCard(
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input wire isoReset,
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input wire isoReset,
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input wire isoClk,
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input wire isoClk,
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input wire isoVdd,
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input wire isoVdd,
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inout wire isoSio
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inout wire isoSio
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);
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);
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// Inputs
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// Inputs
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wire [0:0] clkPerCycle=0;
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wire [0:0] clkPerCycle=0;
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reg [7:0] dataIn;
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reg [7:0] dataIn;
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reg nWeDataIn;
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reg nWeDataIn;
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reg nCsDataOut;
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reg nCsDataOut;
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reg nCsStatusOut;
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reg nCsStatusOut;
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// Outputs
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// Outputs
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wire [7:0] dataOut;
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wire [7:0] dataOut;
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wire [7:0] statusOut;
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wire [7:0] statusOut;
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wire serialOut;
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wire serialOut;
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reg [12:0] cyclesPerEtu;
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wire cardIsoClk;//card use its own generated clock (like true UARTs)
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wire cardIsoClk;//card use its own generated clock (like true UARTs)
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HalfDuplexUartIf uartIf (
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HalfDuplexUartIf uartIf (
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.nReset(isoReset),
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.nReset(isoReset),
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.clk(isoClk),
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.clk(isoClk),
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.clkPerCycle(clkPerCycle),
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.clkPerCycle(clkPerCycle),
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.dataIn(dataIn),
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.dataIn(dataIn),
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.nWeDataIn(nWeDataIn),
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.nWeDataIn(nWeDataIn),
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.clocksPerBit(cyclesPerEtu),
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.dataOut(dataOut),
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.dataOut(dataOut),
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.nCsDataOut(nCsDataOut),
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.nCsDataOut(nCsDataOut),
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.statusOut(statusOut),
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.statusOut(statusOut),
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.nCsStatusOut(nCsStatusOut),
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.nCsStatusOut(nCsStatusOut),
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.serialIn(isoSio),
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.serialIn(isoSio),
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.serialOut(serialOut),
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.serialOut(serialOut),
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.comClk(cardIsoClk)
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.comClk(cardIsoClk)
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);
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);
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reg sendAtr;
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reg sendAtr;
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reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
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reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
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reg [7:0] buffer[256+5:0];
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reg [7:0] buffer[256+5:0];
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localparam CLA_I= 8*4;
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localparam CLA_I= 8*4;
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localparam INS_I= 8*3;
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localparam INS_I= 8*3;
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localparam P1_I = 8*2;
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localparam P1_I = 8*2;
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localparam P2_I = 8*1;
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localparam P2_I = 8*1;
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localparam P3_I = 0;
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localparam P3_I = 0;
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reg [CLA_I+7:0] tpduHeader;
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reg [CLA_I+7:0] tpduHeader;
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wire COM_statusOut=statusOut;
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wire COM_statusOut=statusOut;
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wire COM_clk=isoClk;
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wire COM_clk=isoClk;
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integer COM_errorCnt;
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integer COM_errorCnt;
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wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
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wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
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assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
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assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
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`include "ComDriverTasks.v"
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`include "ComDriverTasks.v"
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assign isoSio = isTx ? serialOut : 1'bz;
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assign isoSio = isTx ? serialOut : 1'bz;
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/*T=0 card model
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/*T=0 card model
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ATR:
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ATR:
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3B 00
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3B 00
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Implemented commands:
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Implemented commands:
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write buffer:
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write buffer:
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tpdu: 00 0C 00 00 LC data
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tpdu: 00 0C 00 00 LC data
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sw: 90 00
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sw: 90 00
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read buffer:
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read buffer:
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tpdu: 00 0A 00 00 LE
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tpdu: 00 0A 00 00 LE
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response: data
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response: data
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sw: 90 00
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sw: 90 00
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any other:
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any other:
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sw: 69 86
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sw: 69 86
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*/
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*/
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task sendAckByte;
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task sendAckByte;
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sendByte(tpduHeader[INS_I+7:INS_I]);
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sendByte(tpduHeader[INS_I+7:INS_I]);
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endtask
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endtask
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task writeBufferCmd;
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task writeBufferCmd;
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integer i;
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integer i;
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begin
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begin
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sendAckByte;
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sendAckByte;
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for(i=0;i<tpduHeader[P3_I+7:P3_I];i=i+1) begin
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for(i=0;i<tpduHeader[P3_I+7:P3_I];i=i+1) begin
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receiveByte(buffer[i]);
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receiveByte(buffer[i]);
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end
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end
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sendWord(16'h9000);
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sendWord(16'h9000);
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end
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end
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endtask
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endtask
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task readBufferCmd;
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task readBufferCmd;
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integer i;
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integer i;
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integer le;
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integer le;
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begin
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begin
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sendAckByte;
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sendAckByte;
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le=tpduHeader[P3_I+7:P3_I];
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le=tpduHeader[P3_I+7:P3_I];
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if(0==le) le=256;
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if(0==le) le=256;
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for(i=0;i<le;i=i+1) begin
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for(i=0;i<le;i=i+1) begin
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sendByte(buffer[i]);
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sendByte(buffer[i]);
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end
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end
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sendWord(16'h9000);
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sendWord(16'h9000);
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end
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end
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endtask
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endtask
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integer i;
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integer i;
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always @(posedge isoClk, negedge isoReset) begin
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always @(posedge isoClk, negedge isoReset) begin
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if(~isoReset) begin
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if(~isoReset) begin
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nWeDataIn<=1'b1;
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nWeDataIn<=1'b1;
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nCsDataOut<=1'b1;
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nCsDataOut<=1'b1;
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nCsStatusOut<=1'b1;
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nCsStatusOut<=1'b1;
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tsCnt<=9'b0;
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tsCnt<=9'b0;
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sendAtr<=1'b1;
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sendAtr<=1'b1;
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cyclesPerEtu <= 13'd372-1'b1;
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end else if(tsCnt!=9'd400) begin
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end else if(tsCnt!=9'd400) begin
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tsCnt <= tsCnt + 1'b1;
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tsCnt <= tsCnt + 1'b1;
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end else if(sendAtr) begin
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end else if(sendAtr) begin
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sendAtr<=1'b0;
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sendAtr<=1'b0;
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sendByte(8'h3B);
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sendByte(8'h3B);
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sendByte(8'h00);
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sendByte(8'h00);
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waitEndOfTx;
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waitEndOfTx;
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end else begin
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end else begin
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//get tpdu
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//get tpdu
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for(i=0;i<5;i=i+1)
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for(i=0;i<5;i=i+1)
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receiveByte(tpduHeader[(CLA_I-(i*8))+:8]);
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receiveByte(tpduHeader[(CLA_I-(i*8))+:8]);
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//dispatch
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//dispatch
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case(tpduHeader[7+CLA_I:P2_I])
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case(tpduHeader[7+CLA_I:P2_I])
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32'h000C0000: writeBufferCmd;
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32'h000C0000: writeBufferCmd;
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32'h000A0000: readBufferCmd;
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32'h000A0000: readBufferCmd;
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default: sendWord(16'h6986);
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default: sendWord(16'h6986);
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endcase
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endcase
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end
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end
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end
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end
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endmodule
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endmodule
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