`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`default_nettype none
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`default_nettype none
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|
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module Iso7816_3_t0_analyzer(
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module Iso7816_3_t0_analyzer(
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input wire nReset,
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input wire nReset,
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input wire clk,
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input wire clk,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire isoReset,
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input wire isoReset,
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input wire isoClk,
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input wire isoClk,
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input wire isoVdd,
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input wire isoVdd,
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input wire isoSio,
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input wire isoSio,
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output reg [3:0] fiCode,
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output reg [3:0] fiCode,
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output reg [3:0] diCode,
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output reg [3:0] diCode,
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output wire [12:0] fi,
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output wire [12:0] fi,
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output wire [7:0] di,
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output wire [7:0] di,
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output wire [12:0] cyclesPerEtu,
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output wire [12:0] cyclesPerEtu,
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output wire [7:0] fMax,
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output wire [7:0] fMax,
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output wire isActivated,
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output wire isActivated,
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output wire tsReceived,
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output wire tsReceived,
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output wire tsError,
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output wire tsError,
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output wire useIndirectConvention,
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output wire useIndirectConvention,
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output wire atrIsEarly,//high if TS received before 400 cycles after reset release
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output wire atrIsEarly,//high if TS received before 400 cycles after reset release
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output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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output reg [3:0] atrK,//number of historical bytes
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output reg [3:0] atrK,//number of historical bytes
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output reg atrHasTck,
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output reg atrHasTck,
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output reg atrCompleted,
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output reg atrCompleted,
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output reg useT0,
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output reg useT0,
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output reg useT1,
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output reg useT1,
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output reg useT15,
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output reg useT15,
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output reg waitCardTx,
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output reg waitCardTx,
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output reg waitTermTx,
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output reg waitTermTx,
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output reg cardTx,
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output reg cardTx,
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output reg termTx,
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output reg termTx,
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output wire guardTime,
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output wire guardTime,
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output wire overrunError,
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output wire overrunError,
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output wire frameError,
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output wire frameError,
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output reg [7:0] lastByte,
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output reg [7:0] lastByte,
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output reg [31:0] bytesCnt
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output reg [31:0] bytesCnt
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);
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);
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parameter DIVIDER_WIDTH = 1;
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parameter DIVIDER_WIDTH = 1;
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|
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reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
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reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
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|
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reg [7:0] buffer[256+5:0];
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reg [7:0] buffer[256+5:0];
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localparam CLA_I= 8*4;
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localparam CLA_I= 8*4;
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localparam INS_I= 8*3;
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localparam INS_I= 8*3;
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localparam P1_I = 8*2;
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localparam P1_I = 8*2;
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localparam P2_I = 8*1;
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localparam P2_I = 8*1;
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localparam P3_I = 0;
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localparam P3_I = 0;
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reg [CLA_I+7:0] tpduHeader;
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reg [CLA_I+7:0] tpduHeader;
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|
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//wire COM_clk=isoClk;
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//wire COM_clk=isoClk;
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//integer COM_errorCnt;
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//integer COM_errorCnt;
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//wire txPending=1'b0;
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//wire txPending=1'b0;
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//wire txRun=1'b0;
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//wire txRun=1'b0;
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|
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wire rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;
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wire rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;
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assign overrunErrorFlag = overrunError;
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assign overrunErrorFlag = overrunError;
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assign frameErrorFlag = frameError;
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assign frameErrorFlag = frameError;
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|
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wire [7:0] rxData;
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wire [7:0] rxData;
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reg ackFlags;
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reg ackFlags;
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|
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wire msbFirst = useIndirectConvention;
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wire msbFirst = useIndirectConvention;
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wire sioHighValue = ~useIndirectConvention;
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wire sioHighValue = ~useIndirectConvention;
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wire oddParity = 1'b0;
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wire oddParity = 1'b0;
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|
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wire [7:0] dataOut = sioHighValue ? rxData : ~rxData;
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wire [7:0] dataOut = sioHighValue ? rxData : ~rxData;
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//`include "ComRxDriverTasks.v"
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//`include "ComRxDriverTasks.v"
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|
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wire endOfRx;
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wire endOfRx;
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|
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wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte
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wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte
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|
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RxCoreSelfContained #(
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RxCoreSelfContained #(
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.DIVIDER_WIDTH(DIVIDER_WIDTH),
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.DIVIDER_WIDTH(DIVIDER_WIDTH),
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.CLOCK_PER_BIT_WIDTH(4'd13),
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.CLOCK_PER_BIT_WIDTH(4'd13),
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.PRECISE_STOP_BIT(1'b1))
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.PRECISE_STOP_BIT(1'b1))
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rxCore (
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rxCore (
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.dataOut(rxData),
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.dataOut(rxData),
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.overrunErrorFlag(overrunError),
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.overrunErrorFlag(overrunError),
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.dataOutReadyFlag(bufferFull),
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.dataOutReadyFlag(bufferFull),
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.frameErrorFlag(frameError),
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.frameErrorFlag(frameError),
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.endOfRx(endOfRx),
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.endOfRx(endOfRx),
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.run(rxRun),
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.run(rxRun),
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.startBit(rxStartBit),
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.startBit(rxStartBit),
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.stopBit(guardTime),
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.stopBit(guardTime),
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.clkPerCycle(clkPerCycle),
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.clkPerCycle(clkPerCycle),
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.clocksPerBit(cyclesPerEtu-1),
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.clocksPerBit(cyclesPerEtu-1),
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.stopBit2(stopBit2),
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.stopBit2(stopBit2),
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.oddParity(oddParity),
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.oddParity(oddParity),
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.msbFirst(msbFirst),
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.msbFirst(msbFirst),
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.ackFlags(ackFlags),
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.ackFlags(ackFlags),
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.serialIn(isoSio),
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.serialIn(isoSio),
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.comClk(isoClk),
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.comClk(isoClk),
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.clk(clk),
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.clk(clk),
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.nReset(nReset)
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.nReset(nReset)
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);
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);
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|
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TsAnalyzer tsAnalyzer(
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TsAnalyzer tsAnalyzer(
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.nReset(nReset),
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.nReset(nReset),
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.isoReset(isoReset),
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.isoReset(isoReset),
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.isoClk(isoClk),
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.isoClk(isoClk),
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.isoVdd(isoVdd),
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.isoVdd(isoVdd),
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.isoSio(isoSio),
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.isoSio(isoSio),
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.endOfRx(endOfRx),
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.endOfRx(endOfRx),
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.rxData(rxData),
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.rxData(rxData),
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.isActivated(isActivated),
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.isActivated(isActivated),
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.tsReceived(tsReceived),
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.tsReceived(tsReceived),
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.tsError(tsError),
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.tsError(tsError),
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.atrIsEarly(atrIsEarly),
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.atrIsEarly(atrIsEarly),
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.atrIsLate(atrIsLate),
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.atrIsLate(atrIsLate),
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.useIndirectConvention(useIndirectConvention)
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.useIndirectConvention(useIndirectConvention)
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);
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);
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|
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FiDiAnalyzer fiDiAnalyzer(
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FiDiAnalyzer fiDiAnalyzer(
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.fiCode(fiCode),
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.fiCode(fiCode),
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.diCode(diCode),
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.diCode(diCode),
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.fi(fi),
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.fi(fi),
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.di(di),
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.di(di),
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.cyclesPerEtu(cyclesPerEtu),
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.cyclesPerEtu(cyclesPerEtu),
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.fMax(fMax)
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.fMax(fMax)
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);
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);
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|
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wire run = rxStartBit | rxRun;
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wire run = rxStartBit | rxRun;
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localparam ATR_T0 = 0;
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localparam ATR_T0 = 0;
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localparam ATR_TDI = 1;
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localparam ATR_TDI = 1;
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localparam ATR_HISTORICAL = 2;
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localparam ATR_HISTORICAL = 2;
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localparam ATR_TCK = 3;
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localparam ATR_TCK = 3;
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localparam T0_HEADER = 0;
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localparam T0_HEADER = 0;
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localparam T0_PB = 0;
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localparam T0_HEADER_TPDU = 1;
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localparam T0_DATA = 0;
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localparam T0_PB = 2;
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localparam T0_DATA = 3;
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localparam T0_NACK_DATA = 4;
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localparam T0_SW1 = 5;
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localparam T0_SW2 = 6;
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localparam T0_HEADER_PPS = 100;
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|
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integer fsmState;
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integer fsmState;
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|
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reg [11:0] tdiStruct;
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reg [11:0] tdiStruct;
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wire [3:0] tdiCnt;//i+1
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wire [3:0] tdiCnt;//i+1
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wire [7:0] tdiData;//value of TDi
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wire [7:0] tdiData;//value of TDi
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assign {tdiCnt,tdiData}=tdiStruct;
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assign {tdiCnt,tdiData}=tdiStruct;
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|
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wire [1:0] nIfBytes;
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wire [1:0] nIfBytes;
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HammingWeight hammingWeight(.dataIn(tdiData[7:4]), .hammingWeight(nIfBytes));
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HammingWeight hammingWeight(.dataIn(tdiData[7:4]), .hammingWeight(nIfBytes));
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reg [7:0] tempBytesCnt;
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reg [7:0] tempBytesCnt;
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always @(posedge isoClk, negedge nReset) begin
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always @(posedge isoClk, negedge nReset) begin
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if(~nReset) begin
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if(~nReset) begin
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lastByte<=8'b0;
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lastByte<=8'b0;
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ackFlags<=1'b0;
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ackFlags<=1'b0;
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bytesCnt<=32'b0;
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bytesCnt<=32'b0;
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end else if(ackFlags) begin
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end else if(ackFlags) begin
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ackFlags<=1'b0;
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ackFlags<=1'b0;
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end else if(frameErrorFlag|bufferFull) begin
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end else if(frameErrorFlag|bufferFull) begin
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lastByte<=dataOut;
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lastByte<=dataOut;
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ackFlags<=1'b1;
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ackFlags<=1'b1;
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bytesCnt<=bytesCnt+1'b1;
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bytesCnt<=bytesCnt+1'b1;
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end
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end
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end
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end
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always @(posedge isoClk, negedge nReset) begin
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always @(posedge isoClk, negedge nReset) begin
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if(~nReset) begin
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if(~nReset) begin
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fiCode<=4'b0001;
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fiCode<=4'b0001;
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diCode<=4'b0001;
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diCode<=4'b0001;
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useT0<=1'b1;
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useT0<=1'b1;
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useT1<=1'b0;
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useT1<=1'b0;
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useT15<=1'b0;
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useT15<=1'b0;
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waitCardTx<=1'b0;
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{waitCardTx,waitTermTx}<=2'b00;
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waitTermTx<=1'b0;
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fsmState<=ATR_TDI;
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fsmState<=ATR_TDI;
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atrHasTck<=1'b0;
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atrHasTck<=1'b0;
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tempBytesCnt<=8'h0;
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tempBytesCnt<=8'h0;
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tdiStruct<=12'h0;
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tdiStruct<=12'h0;
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atrCompleted<=1'b0;
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atrCompleted<=1'b0;
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atrK<=4'b0;
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end else if(isActivated) begin
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end else if(isActivated) begin
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if(~tsReceived) begin
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if(~tsReceived) begin
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waitCardTx<=1'b1;
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{waitCardTx,waitTermTx}<=2'b10;
|
end else if(~atrCompleted) begin
|
end else if(~atrCompleted) begin
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//ATR analysis
|
//ATR analysis
|
case(fsmState)
|
case(fsmState)
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ATR_TDI: begin
|
ATR_TDI: begin
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if(endOfRx) begin
|
if(endOfRx) begin
|
if(tempBytesCnt==nIfBytes) begin //TDi bytes
|
if(tempBytesCnt==nIfBytes) begin //TDi bytes
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tempBytesCnt <= 2'h0;
|
tempBytesCnt <= 2'h0;
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tdiStruct <= {tdiCnt+1,dataOut};
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tdiStruct <= {tdiCnt+1,dataOut};
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if(4'h0==tdiCnt) begin//this is T0
|
if(4'h0==tdiCnt) begin//this is T0
|
atrK <= dataOut[3:0];
|
atrK <= dataOut[3:0];
|
fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :
|
fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :
|
(4'b0!=dataOut[3:0]) ? ATR_HISTORICAL : T0_HEADER;
|
(4'b0!=dataOut[3:0]) ? ATR_HISTORICAL : T0_HEADER;
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end else begin//TDi, i from 1 to 15
|
end else begin//TDi, i from 1 to 15
|
fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :
|
fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :
|
(4'b0!=atrK) ? ATR_HISTORICAL : T0_HEADER;
|
(4'b0!=atrK) ? ATR_HISTORICAL : T0_HEADER;
|
end
|
end
|
|
if(12'h0=={dataOut,atrK}) begin
|
|
atrCompleted <= 1'b1;
|
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{waitCardTx,waitTermTx}<=2'b01;
|
|
end
|
end else begin //TA, TB or TC bytes
|
end else begin //TA, TB or TC bytes
|
//TODO: get relevant info
|
//TODO: get relevant info
|
tempBytesCnt <= tempBytesCnt+1;
|
tempBytesCnt <= tempBytesCnt+1;
|
end
|
end
|
end
|
end
|
end
|
end
|
ATR_HISTORICAL: begin
|
ATR_HISTORICAL: begin
|
if(endOfRx) begin
|
if(endOfRx) begin
|
if(tempBytesCnt==atrK) begin
|
if(tempBytesCnt==atrK) begin
|
|
tempBytesCnt <= 8'h0;
|
|
if(atrHasTck) begin
|
|
fsmState <= ATR_TCK;
|
|
end else begin
|
atrCompleted <= ~atrHasTck;
|
atrCompleted <= ~atrHasTck;
|
fsmState <= atrHasTck ? ATR_TCK : T0_HEADER;
|
{waitCardTx,waitTermTx}<=2'b10;
|
|
fsmState <= T0_HEADER;
|
|
end
|
end else begin
|
end else begin
|
tempBytesCnt <= tempBytesCnt+1;
|
tempBytesCnt <= tempBytesCnt+1;
|
end
|
end
|
end
|
end
|
end
|
end
|
ATR_TCK: begin
|
ATR_TCK: begin
|
if(endOfRx) begin
|
if(endOfRx) begin
|
//TODO:check
|
//TODO:check
|
atrCompleted <= 1'b1;
|
atrCompleted <= 1'b1;
|
|
{waitCardTx,waitTermTx}<=2'b10;
|
fsmState <= T0_HEADER;
|
fsmState <= T0_HEADER;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end else if(useT0) begin
|
end else if(useT0) begin
|
//T=0 cmd/response monitoring state machine
|
//T=0 cmd/response monitoring state machine
|
|
case(fsmState)
|
|
T0_HEADER: begin
|
|
if(endOfRx) begin
|
|
tpduHeader[CLA_I+:8]<=dataOut;
|
|
tempBytesCnt <= 1;
|
|
if(8'hFF==dataOut)
|
|
fsmState <= T0_HEADER_PPS;//TODO
|
|
else
|
|
fsmState <= T0_HEADER_TPDU;
|
|
end
|
|
end
|
|
T0_HEADER_TPDU: begin
|
|
if(endOfRx) begin
|
|
tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]<=dataOut;
|
|
if(4==tempBytesCnt) begin
|
|
tempBytesCnt <= 8'h0;
|
|
fsmState <= T0_PB;
|
|
{waitCardTx,waitTermTx}<=2'b10;
|
|
end else begin
|
|
tempBytesCnt <= tempBytesCnt+1;
|
|
end
|
|
end
|
|
end
|
|
T0_PB: begin
|
|
if(endOfRx) begin
|
|
case(dataOut[7:4])
|
|
4'h6: begin
|
|
fsmState <= (4'h0==dataOut[3:0]) ? T0_PB : T0_SW2;
|
|
end
|
|
4'h9: begin
|
|
fsmState <= T0_SW2;
|
|
end
|
|
default: begin
|
|
case(dataOut)
|
|
tpduHeader[INS_I+:8]: begin//ACK
|
|
fsmState <= T0_DATA;
|
|
{waitCardTx,waitTermTx}<=2'b11;
|
|
end
|
|
~tpduHeader[INS_I+:8]: begin//NACK
|
|
fsmState <= T0_NACK_DATA;
|
|
{waitCardTx,waitTermTx}<=2'b11;
|
|
end
|
|
default: begin //invalid
|
|
//TODO
|
|
end
|
|
endcase
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
T0_NACK_DATA: begin
|
|
if(endOfRx) begin
|
|
fsmState <= T0_PB;
|
|
{waitCardTx,waitTermTx}<=2'b10;
|
|
tempBytesCnt <= tempBytesCnt+1;
|
|
end
|
|
end
|
|
T0_SW1: begin
|
|
if(endOfRx) begin
|
|
//TODO:check != 60 but equal to 6x or 9x
|
|
fsmState <= T0_SW2;
|
|
{waitCardTx,waitTermTx}<=2'b10;
|
|
end
|
|
end
|
|
T0_SW2: begin
|
|
if(endOfRx) begin
|
|
fsmState <= T0_HEADER;
|
|
{waitCardTx,waitTermTx}<=2'b01;
|
|
end
|
|
end
|
|
T0_DATA: begin
|
|
if(endOfRx) begin
|
|
if(tempBytesCnt==(tpduHeader[P3_I+:8]-1)) begin
|
|
tempBytesCnt <= 0;
|
|
fsmState <= T0_SW1;
|
|
{waitCardTx,waitTermTx}<=2'b10;
|
|
end else begin
|
|
tempBytesCnt <= tempBytesCnt+1;
|
|
end
|
|
end
|
|
end
|
|
endcase
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
reg [1:0] txDir;
|
reg [1:0] txDir;
|
always @(*) begin: errorSigDirectionBlock
|
always @(*) begin: errorSigDirectionBlock
|
if(guardTime & ~isoSio)
|
if(guardTime & ~isoSio)
|
{cardTx, termTx}={txDir[0],txDir[1]};
|
{cardTx, termTx}={txDir[0],txDir[1]};
|
else
|
else
|
{cardTx, termTx}={txDir[1],txDir[0]};
|
{cardTx, termTx}={txDir[1],txDir[0]};
|
end
|
end
|
always @(posedge isoClk, negedge nReset) begin: comDirectionBlock
|
always @(posedge isoClk, negedge nReset) begin: comDirectionBlock
|
if(~nReset | ~run) begin
|
if(~nReset | ~run) begin
|
txDir<=2'b00;
|
txDir<=2'b00;
|
end else begin
|
end else begin
|
if(~guardTime) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here
|
if(~guardTime) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here
|
case({waitCardTx, waitTermTx})
|
case({waitCardTx, waitTermTx})
|
2'b00: txDir<=2'b00;
|
2'b00: txDir<=2'b00;//no one should/is sending
|
2'b01: txDir<=2'b01;
|
2'b01: txDir<=2'b01;//terminal should/is sending
|
2'b10: txDir<=2'b10;
|
2'b10: txDir<=2'b10;//card should/is sending
|
2'b11: txDir<=2'b00;
|
2'b11: txDir<=2'b11;//either card OR terminal should/is sending (we just don't know)
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
|
|
