/*
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/*
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Author: Sebastien Riou (acapola)
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Author: Sebastien Riou (acapola)
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Creation date: 22:16:42 01/10/2011
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Creation date: 22:16:42 01/10/2011
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$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
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$LastChangedDate: 2011-01-29 17:13:49 +0100 (Sat, 29 Jan 2011) $
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$LastChangedBy: acapola $
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$LastChangedBy: acapola $
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$LastChangedRevision: 11 $
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$LastChangedRevision: 12 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/tbIso7816_3_Master.v $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/tbIso7816_3_Master.v $
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This file is under the BSD licence:
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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Copyright (c) 2011, Sebastien Riou
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All rights reserved.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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`default_nettype none
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`default_nettype none
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module tbIso7816_3_Master;
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module tbIso7816_3_Master;
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parameter CLK_PERIOD = 10;//should be %2
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parameter CLK_PERIOD = 10;//should be %2
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// Inputs
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// Inputs
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reg nReset;
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reg nReset;
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reg clk;
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reg clk;
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reg [15:0] clkPerCycle;
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reg [15:0] clkPerCycle;
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reg startActivation;
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reg startActivation;
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reg startDeactivation;
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reg startDeactivation;
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reg [7:0] dataIn;
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reg [7:0] dataIn;
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reg nWeDataIn;
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reg nWeDataIn;
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reg [12:0] cyclesPerEtu;
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reg [12:0] cyclesPerEtu;
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reg nCsDataOut;
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reg nCsDataOut;
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reg nCsStatusOut;
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reg nCsStatusOut;
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// Outputs
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// Outputs
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wire [7:0] dataOut;
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wire [7:0] dataOut;
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wire [7:0] statusOut;
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wire [7:0] statusOut;
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wire isActivated;
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wire isActivated;
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wire useIndirectConvention;
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wire useIndirectConvention;
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wire tsError;
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wire tsError;
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wire tsReceived;
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wire tsReceived;
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wire atrIsEarly;
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wire atrIsEarly;
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wire atrIsLate;
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wire atrIsLate;
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wire isoClk;
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wire isoClk;
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wire isoReset;
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wire isoReset;
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wire isoVdd;
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wire isoVdd;
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//probe outputs
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//probe outputs
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wire probe_termMon;
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wire probe_termMon;
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wire probe_cardMon;
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wire probe_cardMon;
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// Bidirs
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// Bidirs
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wire isoSioTerm;
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wire isoSioTerm;
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wire isoSioCard;
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wire isoSioCard;
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wire COM_statusOut=statusOut;
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wire COM_statusOut=statusOut;
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wire COM_clk=isoClk;
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wire COM_clk=isoClk;
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integer COM_errorCnt;
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integer COM_errorCnt;
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wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
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wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
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assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
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assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
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`include "ComDriverTasks.v"
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`include "ComDriverTasks.v"
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wire [3:0] spy_fiCode;
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wire [3:0] spy_fiCode;
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wire [3:0] spy_diCode;
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wire [3:0] spy_diCode;
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wire [12:0] spy_fi;
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wire [12:0] spy_fi;
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wire [7:0] spy_di;
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wire [7:0] spy_di;
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wire [12:0] spy_cyclesPerEtu;
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wire [12:0] spy_cyclesPerEtu;
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wire [7:0] spy_fMax;
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wire [7:0] spy_fMax;
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wire spy_isActivated,spy_tsReceived,spy_tsError;
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wire spy_isActivated,spy_tsReceived,spy_tsError;
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wire spy_useIndirectConvention,spy_atrIsEarly,spy_atrIsLate;
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wire spy_useIndirectConvention,spy_atrIsEarly,spy_atrIsLate;
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wire [3:0] spy_atrK;
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wire [3:0] spy_atrK;
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wire spy_atrHasTck,spy_atrCompleted;
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wire spy_atrHasTck,spy_atrCompleted;
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wire spy_useT0,spy_useT1,spy_useT15,spy_waitCardTx,spy_waitTermTx,spy_cardTx,spy_termTx,spy_guardTime;
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wire spy_useT0,spy_useT1,spy_useT15,spy_waitCardTx,spy_waitTermTx,spy_cardTx,spy_termTx,spy_guardTime;
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wire spy_overrunError,spy_frameError;
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wire spy_overrunError,spy_frameError;
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wire [7:0] spy_lastByte;
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wire [7:0] spy_lastByte;
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wire [31:0] spy_bytesCnt;
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wire [31:0] spy_bytesCnt;
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// Instantiate the Unit Under Test (UUT)
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// Instantiate the Unit Under Test (UUT)
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Iso7816_3_Master uut (
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Iso7816_3_Master uut (
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.nReset(nReset),
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.nReset(nReset),
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.clk(clk),
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.clk(clk),
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.clkPerCycle(clkPerCycle),
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.clkPerCycle(clkPerCycle),
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.startActivation(startActivation),
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.startActivation(startActivation),
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.startDeactivation(startDeactivation),
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.startDeactivation(startDeactivation),
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.dataIn(dataIn),
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.dataIn(dataIn),
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.nWeDataIn(nWeDataIn),
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.nWeDataIn(nWeDataIn),
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.cyclesPerEtu(cyclesPerEtu),
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.cyclesPerEtu(cyclesPerEtu),
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.dataOut(dataOut),
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.dataOut(dataOut),
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.nCsDataOut(nCsDataOut),
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.nCsDataOut(nCsDataOut),
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.statusOut(statusOut),
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.statusOut(statusOut),
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.nCsStatusOut(nCsStatusOut),
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.nCsStatusOut(nCsStatusOut),
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.isActivated(isActivated),
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.isActivated(isActivated),
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.useIndirectConvention(useIndirectConvention),
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.useIndirectConvention(useIndirectConvention),
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.tsError(tsError),
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.tsError(tsError),
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.tsReceived(tsReceived),
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.tsReceived(tsReceived),
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.atrIsEarly(atrIsEarly),
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.atrIsEarly(atrIsEarly),
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.atrIsLate(atrIsLate),
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.atrIsLate(atrIsLate),
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.isoSio(isoSioTerm),
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.isoSio(isoSioTerm),
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.isoClk(isoClk),
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.isoClk(isoClk),
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.isoReset(isoReset),
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.isoReset(isoReset),
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.isoVdd(isoVdd)
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.isoVdd(isoVdd)
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);
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);
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DummyCard card(
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DummyCard card(
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.isoReset(isoReset),
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.isoReset(isoReset),
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.isoClk(isoClk),
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.isoClk(isoClk),
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.isoVdd(isoVdd),
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.isoVdd(isoVdd),
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.isoSio(isoSioCard)
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.isoSio(isoSioCard)
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);
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);
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Iso7816_directionProbe probe(
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Iso7816_directionProbe probe(
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.isoSioTerm(isoSioTerm),
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.isoSioTerm(isoSioTerm),
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.isoSioCard(isoSioCard),
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.isoSioCard(isoSioCard),
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.termMon(probe_termMon),
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.termMon(probe_termMon),
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.cardMon(probe_cardMon)
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.cardMon(probe_cardMon)
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);
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);
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Iso7816_3_t0_analyzer spy (
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Iso7816_3_t0_analyzer spy (
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.nReset(nReset),
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.nReset(nReset),
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.clk(clk),
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.clk(clk),
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.clkPerCycle(clkPerCycle[0]),
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.clkPerCycle(clkPerCycle[0]),
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.isoReset(isoReset),
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.isoReset(isoReset),
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.isoClk(isoClk),
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.isoClk(isoClk),
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.isoVdd(isoVdd),
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.isoVdd(isoVdd),
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.isoSioTerm(probe_termMon),
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.isoSioTerm(probe_termMon),
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.isoSioCard(probe_cardMon),
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.isoSioCard(probe_cardMon),
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.useDirectionProbe(1'b1),
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.useDirectionProbe(1'b1),
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.fiCode(spy_fiCode),
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.fiCode(spy_fiCode),
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.diCode(spy_diCode),
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.diCode(spy_diCode),
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.fi(spy_fi),
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.fi(spy_fi),
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.di(spy_di),
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.di(spy_di),
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.cyclesPerEtu(spy_cyclesPerEtu),
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.cyclesPerEtu(spy_cyclesPerEtu),
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.fMax(spy_fMax),
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.fMax(spy_fMax),
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.isActivated(spy_isActivated),
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.isActivated(spy_isActivated),
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.tsReceived(spy_tsReceived),
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.tsReceived(spy_tsReceived),
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.tsError(spy_tsError),
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.tsError(spy_tsError),
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.useIndirectConvention(spy_useIndirectConvention),
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.useIndirectConvention(spy_useIndirectConvention),
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.atrIsEarly(spy_atrIsEarly),
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.atrIsEarly(spy_atrIsEarly),
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.atrIsLate(spy_atrIsLate),
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.atrIsLate(spy_atrIsLate),
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.atrK(spy_atrK),
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.atrK(spy_atrK),
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.atrHasTck(spy_atrHasTck),
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.atrHasTck(spy_atrHasTck),
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.atrCompleted(spy_atrCompleted),
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.atrCompleted(spy_atrCompleted),
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.useT0(spy_useT0),
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.useT0(spy_useT0),
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.useT1(spy_useT1),
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.useT1(spy_useT1),
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.useT15(spy_useT15),
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.useT15(spy_useT15),
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.waitCardTx(spy_waitCardTx),
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.waitCardTx(spy_waitCardTx),
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.waitTermTx(spy_waitTermTx),
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.waitTermTx(spy_waitTermTx),
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.cardTx(spy_cardTx),
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.cardTx(spy_cardTx),
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.termTx(spy_termTx),
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.termTx(spy_termTx),
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.guardTime(spy_guardTime),
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.guardTime(spy_guardTime),
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.overrunError(spy_overrunError),
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.overrunError(spy_overrunError),
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.frameError(spy_frameError),
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.frameError(spy_frameError),
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.lastByte(spy_lastByte),
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.lastByte(spy_lastByte),
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.bytesCnt(spy_bytesCnt)
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.bytesCnt(spy_bytesCnt)
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);
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);
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integer tbErrorCnt;
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integer tbErrorCnt;
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reg tbTestSequenceDone;
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reg tbTestSequenceDone;
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initial begin
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initial begin
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// Initialize Inputs
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// Initialize Inputs
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tbErrorCnt=0;
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tbErrorCnt=0;
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COM_errorCnt=0;
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COM_errorCnt=0;
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nReset = 0;
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nReset = 0;
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clk = 0;
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clk = 0;
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clkPerCycle = 0;
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clkPerCycle = 0;
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startActivation = 0;
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startActivation = 0;
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startDeactivation = 0;
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startDeactivation = 0;
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dataIn = 0;
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dataIn = 0;
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nWeDataIn = 1'b1;
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nWeDataIn = 1'b1;
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cyclesPerEtu = 372-1;
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cyclesPerEtu = 372-1;
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nCsDataOut = 1'b1;
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nCsDataOut = 1'b1;
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nCsStatusOut = 1'b1;
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nCsStatusOut = 1'b1;
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// Wait 100 ns for global reset to finish
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// Wait 100 ns for global reset to finish
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#100;
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#100;
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nReset = 1;
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nReset = 1;
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// Add stimulus here
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// Add stimulus here
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#100
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#100
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startActivation = 1'b1;
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startActivation = 1'b1;
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wait(isActivated);
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wait(isActivated);
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wait(tsReceived);
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wait(tsReceived);
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if(atrIsEarly) begin
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if(atrIsEarly) begin
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$display("ERROR: ATR is early");
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$display("ERROR: ATR is early");
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tbErrorCnt=tbErrorCnt+1;
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tbErrorCnt=tbErrorCnt+1;
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end
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end
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if(atrIsLate) begin
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if(atrIsLate) begin
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$display("ERROR: ATR is late");
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$display("ERROR: ATR is late");
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tbErrorCnt=tbErrorCnt+1;
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tbErrorCnt=tbErrorCnt+1;
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end
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end
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@(posedge clk);
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@(posedge clk);
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while((txRun===1'b1)||(rxRun===1'b1)||(rxStartBit===1'b1)) begin
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while((txRun===1'b1)||(rxRun===1'b1)||(rxStartBit===1'b1)) begin
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while((txRun===1'b1)||(rxRun===1'b1)||(rxStartBit===1'b1)) begin
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while((txRun===1'b1)||(rxRun===1'b1)||(rxStartBit===1'b1)) begin
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@(posedge clk);
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@(posedge clk);
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end
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end
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@(posedge clk);
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@(posedge clk);
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end
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end
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if(1'b1!==tbTestSequenceDone) begin
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if(1'b1!==tbTestSequenceDone) begin
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$display("ERROR: Two cycle pause in communication detected, stop simulation, time=",$time);
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$display("ERROR: Two cycle pause in communication detected, stop simulation, time=",$time);
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#(CLK_PERIOD*372*12);
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#(CLK_PERIOD*372*12);
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$finish;
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$finish;
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end
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end
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end
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end
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//T=0 tpdu stimuli
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//T=0 tpdu stimuli
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initial begin
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initial begin
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tbTestSequenceDone=1'b0;
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tbTestSequenceDone=1'b0;
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receiveAndCheckHexBytes("3B00");
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receiveAndCheckHexBytes("3B00");
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sendHexBytes("FF109778");
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receiveAndCheckHexBytes("FF109778");
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cyclesPerEtu=8-1;
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sendHexBytes("000C000001");
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sendHexBytes("000C000001");
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receiveAndCheckHexBytes("0C");
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receiveAndCheckHexBytes("0C");
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sendHexBytes("55");
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sendHexBytes("55");
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receiveAndCheckHexBytes("9000");
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receiveAndCheckHexBytes("9000");
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tbTestSequenceDone=1'b1;
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tbTestSequenceDone=1'b1;
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$display("SUCCESS: test sequence completed.");
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$display("SUCCESS: test sequence completed.");
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#(CLK_PERIOD*372*12);
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#(CLK_PERIOD*372*12);
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$finish;
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$finish;
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end
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end
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initial begin
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initial begin
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// timeout
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// timeout
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#10000000;
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#10000000;
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tbErrorCnt=tbErrorCnt+1;
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tbErrorCnt=tbErrorCnt+1;
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$display("ERROR: timeout expired");
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$display("ERROR: timeout expired");
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#10;
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#10;
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$finish;
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$finish;
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end
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end
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always
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always
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#(CLK_PERIOD/2) clk = ! clk;
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#(CLK_PERIOD/2) clk = ! clk;
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endmodule
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endmodule
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`default_nettype wire
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`default_nettype wire
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