`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`default_nettype none
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 22:16:42 01/10/2011
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// Create Date: 22:16:42 01/10/2011
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// Design Name: Iso7816_3_Master
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// Design Name: Iso7816_3_Master
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// Module Name: tbIso7816_3_Master.v
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// Module Name: tbIso7816_3_Master.v
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// Project Name: Uart
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// Project Name: Uart
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// Target Device:
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// Target Device:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Verilog Test Fixture created by ISE for module: Iso7816_3_Master
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// Verilog Test Fixture created by ISE for module: Iso7816_3_Master
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module tbIso7816_3_Master;
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module tbIso7816_3_Master;
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parameter CLK_PERIOD = 10;//should be %2
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parameter CLK_PERIOD = 10;//should be %2
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// Inputs
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// Inputs
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reg nReset;
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reg nReset;
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reg clk;
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reg clk;
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reg [15:0] clkPerCycle;
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reg [15:0] clkPerCycle;
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reg startActivation;
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reg startActivation;
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reg startDeactivation;
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reg startDeactivation;
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reg [7:0] dataIn;
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reg [7:0] dataIn;
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reg nWeDataIn;
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reg nWeDataIn;
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reg [12:0] cyclePerEtu;
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reg [12:0] cyclePerEtu;
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reg nCsDataOut;
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reg nCsDataOut;
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reg nCsStatusOut;
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reg nCsStatusOut;
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// Outputs
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// Outputs
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wire [7:0] dataOut;
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wire [7:0] dataOut;
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wire [7:0] statusOut;
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wire [7:0] statusOut;
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wire isActivated;
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wire isActivated;
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wire useIndirectConvention;
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wire useIndirectConvention;
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wire tsError;
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wire tsError;
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wire tsReceived;
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wire tsReceived;
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wire atrIsEarly;
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wire atrIsEarly;
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wire atrIsLate;
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wire atrIsLate;
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wire isoClk;
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wire isoClk;
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wire isoReset;
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wire isoReset;
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wire isoVdd;
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wire isoVdd;
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// Bidirs
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// Bidirs
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wire isoSio;
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wire isoSio;
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wire COM_statusOut=statusOut;
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wire COM_clk=isoClk;
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integer COM_errorCnt;
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wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
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assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
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`include "ComDriverTasks.v"
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// Instantiate the Unit Under Test (UUT)
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// Instantiate the Unit Under Test (UUT)
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Iso7816_3_Master uut (
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Iso7816_3_Master uut (
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.nReset(nReset),
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.nReset(nReset),
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.clk(clk),
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.clk(clk),
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.clkPerCycle(clkPerCycle),
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.clkPerCycle(clkPerCycle),
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.startActivation(startActivation),
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.startActivation(startActivation),
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.startDeactivation(startDeactivation),
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.startDeactivation(startDeactivation),
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.dataIn(dataIn),
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.dataIn(dataIn),
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.nWeDataIn(nWeDataIn),
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.nWeDataIn(nWeDataIn),
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.cyclePerEtu(cyclePerEtu),
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.cyclePerEtu(cyclePerEtu),
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.dataOut(dataOut),
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.dataOut(dataOut),
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.nCsDataOut(nCsDataOut),
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.nCsDataOut(nCsDataOut),
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.statusOut(statusOut),
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.statusOut(statusOut),
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.nCsStatusOut(nCsStatusOut),
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.nCsStatusOut(nCsStatusOut),
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.isActivated(isActivated),
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.isActivated(isActivated),
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.useIndirectConvention(useIndirectConvention),
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.useIndirectConvention(useIndirectConvention),
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.tsError(tsError),
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.tsError(tsError),
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.tsReceived(tsReceived),
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.tsReceived(tsReceived),
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.atrIsEarly(atrIsEarly),
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.atrIsEarly(atrIsEarly),
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.atrIsLate(atrIsLate),
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.atrIsLate(atrIsLate),
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.isoSio(isoSio),
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.isoSio(isoSio),
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.isoClk(isoClk),
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.isoClk(isoClk),
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.isoReset(isoReset),
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.isoReset(isoReset),
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.isoVdd(isoVdd)
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.isoVdd(isoVdd)
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);
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);
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DummyCard card(
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DummyCard card(
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.isoReset(isoReset),
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.isoReset(isoReset),
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.isoClk(isoClk),
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.isoClk(isoClk),
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.isoVdd(isoVdd),
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.isoVdd(isoVdd),
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.isoSio(isoSio)
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.isoSio(isoSio)
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);
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);
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integer tbErrorCnt;
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integer tbErrorCnt;
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initial begin
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initial begin
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// Initialize Inputs
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// Initialize Inputs
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COM_errorCnt=0;
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nReset = 0;
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nReset = 0;
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clk = 0;
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clk = 0;
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clkPerCycle = 0;
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clkPerCycle = 0;
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startActivation = 0;
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startActivation = 0;
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startDeactivation = 0;
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startDeactivation = 0;
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dataIn = 0;
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dataIn = 0;
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nWeDataIn = 0;
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nWeDataIn = 1'b1;
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cyclePerEtu = 0;
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cyclePerEtu = 0;
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nCsDataOut = 0;
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nCsDataOut = 1'b1;
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nCsStatusOut = 0;
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nCsStatusOut = 1'b1;
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// Wait 100 ns for global reset to finish
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// Wait 100 ns for global reset to finish
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#100;
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#100;
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nReset = 1;
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nReset = 1;
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// Add stimulus here
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// Add stimulus here
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#100
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#100
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startActivation = 1'b1;
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startActivation = 1'b1;
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wait(isActivated);
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wait(isActivated);
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wait(atrIsEarly|atrIsLate);
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wait(tsReceived);
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if(atrIsEarly) begin
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$display("ERROR: ATR is early");
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tbErrorCnt=tbErrorCnt+1;
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end
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if(atrIsLate) begin
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$display("ERROR: ATR is late");
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tbErrorCnt=tbErrorCnt+1;
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end
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@(posedge clk);
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while((txRun===1'b1)||(rxRun===1'b1)||(rxStartBit===1'b1)) begin
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while((txRun===1'b1)||(rxRun===1'b1)||(rxStartBit===1'b1)) begin
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@(posedge clk);
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end
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@(posedge clk);
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end
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$display("Two cycle pause in communication detected, stop simulation");
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#200
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#200
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$finish;
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$finish;
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end
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end
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//T=0 tpdu stimuli
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initial begin
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receiveAndCheckByte(8'h3B);
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receiveAndCheckByte(8'h00);
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//sendBytes("000C000001");//would be handy, TODO
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sendByte(8'h00);
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sendByte(8'h0C);
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sendByte(8'h00);
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sendByte(8'h00);
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sendByte(8'h01);
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receiveAndCheckByte(8'h0C);
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//sendBytes("55");
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sendByte(8'h55);
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receiveAndCheckByte(8'h90);
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receiveAndCheckByte(8'h00);
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end
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initial begin
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initial begin
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// timeout
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// timeout
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#10000;
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#100000;
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tbErrorCnt=tbErrorCnt+1;
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tbErrorCnt=tbErrorCnt+1;
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$display("ERROR: timeout expired");
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$display("ERROR: timeout expired");
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#10;
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#10;
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$finish;
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$finish;
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end
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end
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always
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always
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#(CLK_PERIOD/2) clk = ! clk;
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#(CLK_PERIOD/2) clk = ! clk;
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endmodule
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endmodule
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