`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 22:45:51 10/31/2010
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// Create Date: 22:45:51 10/31/2010
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// Design Name: HalfDuplexUartIf
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// Design Name: HalfDuplexUartIf
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// Module Name: tb_HalfDuplexUartIf.v
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// Module Name: tb_HalfDuplexUartIf.v
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// Project Name: Uart
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// Project Name: Uart
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// Target Device:
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// Target Device:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Verilog Test Fixture created by ISE for module: HalfDuplexUartIf
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// Verilog Test Fixture created by ISE for module: HalfDuplexUartIf
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module tb_HalfDuplexUartIf;
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module tb_HalfDuplexUartIf;
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parameter CLK_PERIOD = 10;//should be %2
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parameter CLK_PERIOD = 10;//should be %2
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parameter DIVIDER_WIDTH = 16;
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parameter DIVIDER_WIDTH = 16;
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// Inputs
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// Inputs
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reg nReset;
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reg nReset;
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reg clk;
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reg clk;
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reg [DIVIDER_WIDTH-1:0] clkPerCycle;
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reg [DIVIDER_WIDTH-1:0] clkPerCycle;
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reg [7:0] dataIn;
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reg [7:0] dataIn;
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reg nWeDataIn;
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reg nWeDataIn;
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reg nCsDataOut;
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reg nCsDataOut;
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reg nCsStatusOut;
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reg nCsStatusOut;
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wire serialIn;
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wire serialIn;
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// Outputs
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// Outputs
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wire [7:0] dataOut;
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wire [7:0] dataOut;
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wire [7:0] statusOut;
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wire [7:0] statusOut;
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wire serialOut;
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wire serialOut;
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wire isTx;
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wire isTx;
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// Inputs
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// Inputs
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reg [7:0] dataIn2;
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reg [7:0] dataIn2;
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reg nWeDataIn2;
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reg nWeDataIn2;
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reg nCsDataOut2;
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reg nCsDataOut2;
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reg nCsStatusOut2;
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reg nCsStatusOut2;
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wire serialIn2;
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wire serialIn2;
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// Outputs
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// Outputs
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wire [7:0] dataOut2;
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wire [7:0] dataOut2;
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wire [7:0] statusOut2;
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wire [7:0] statusOut2;
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wire serialOut2;
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wire serialOut2;
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wire isTx2;
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wire isTx2;
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// Bidirs
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// Bidirs
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wire serialLine = isTx ? serialOut : isTx2 ? serialOut2 : 1'bz;
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wire serialLine = isTx ? serialOut : isTx2 ? serialOut2 : 1'bz;
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pullup(serialLine);
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pullup(serialLine);
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assign serialIn = serialLine;
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assign serialIn = serialLine;
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assign serialIn2 = serialLine;
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assign serialIn2 = serialLine;
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// Instantiate the Unit Under Test (UUT)
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// Instantiate the Unit Under Test (UUT)
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HalfDuplexUartIf #(.DIVIDER_WIDTH(DIVIDER_WIDTH))
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HalfDuplexUartIf #(.DIVIDER_WIDTH(DIVIDER_WIDTH))
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uut (
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uut (
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.nReset(nReset),
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.nReset(nReset),
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.clk(clk),
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.clk(clk),
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.clkPerCycle(clkPerCycle),
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.clkPerCycle(clkPerCycle),
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.dataIn(dataIn),
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.dataIn(dataIn),
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.nWeDataIn(nWeDataIn),
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.nWeDataIn(nWeDataIn),
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.dataOut(dataOut),
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.dataOut(dataOut),
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.nCsDataOut(nCsDataOut),
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.nCsDataOut(nCsDataOut),
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.statusOut(statusOut),
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.statusOut(statusOut),
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.nCsStatusOut(nCsStatusOut),
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.nCsStatusOut(nCsStatusOut),
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.serialIn(serialIn),
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.serialIn(serialIn),
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.serialOut(serialOut),
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.serialOut(serialOut),
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.isTx(isTx)
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.isTx(isTx)
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);
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);
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HalfDuplexUartIf #(.DIVIDER_WIDTH(DIVIDER_WIDTH))
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HalfDuplexUartIf #(.DIVIDER_WIDTH(DIVIDER_WIDTH))
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uut2 (
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uut2 (
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.nReset(nReset),
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.nReset(nReset),
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.clk(clk),
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.clk(clk),
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.clkPerCycle(clkPerCycle),
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.clkPerCycle(clkPerCycle),
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.dataIn(dataIn2),
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.dataIn(dataIn2),
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.nWeDataIn(nWeDataIn2),
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.nWeDataIn(nWeDataIn2),
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.dataOut(dataOut2),
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.dataOut(dataOut2),
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.nCsDataOut(nCsDataOut2),
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.nCsDataOut(nCsDataOut2),
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.statusOut(statusOut2),
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.statusOut(statusOut2),
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.nCsStatusOut(nCsStatusOut2),
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.nCsStatusOut(nCsStatusOut2),
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.serialIn(serialIn2),
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.serialIn(serialIn2),
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.serialOut(serialOut2),
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.serialOut(serialOut2),
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.isTx(isTx2)
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.isTx(isTx2)
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);
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);
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integer tbErrorCnt;
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integer tbErrorCnt;
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wire bufferFull = statusOut[0];
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wire bufferFull = statusOut[0];
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wire bufferFull2 = statusOut2[0];
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wire bufferFull2 = statusOut2[0];
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wire txPending = statusOut[6];
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wire txPending = statusOut[6];
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wire txPending2 = statusOut2[6];
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wire txPending2 = statusOut2[6];
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/*//this is sensitive to glitch in combo logic so we cannot use wait(txRun == 0) or @negedge(txRun)...
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/*//this is sensitive to glitch in combo logic so we cannot use wait(txRun == 0) or @negedge(txRun)...
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wire bufferFull = statusOut[0];
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wire bufferFull = statusOut[0];
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wire rxRun = statusOut[5];
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wire rxRun = statusOut[5];
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wire txRun = statusOut[6];
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wire txRun = statusOut[6];
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wire bufferFull2 = statusOut2[0];
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wire bufferFull2 = statusOut2[0];
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wire rxRun2 = statusOut2[5];
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wire rxRun2 = statusOut2[5];
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wire txRun2 = statusOut2[6];
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wire txRun2 = statusOut2[6];
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*/
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*/
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//reg bufferFull ;//already registered
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//reg bufferFull ;//already registered
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reg rxRun ;
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reg rxRun ;
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reg txRun ;
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reg txRun ;
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//reg bufferFull2 ;
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//reg bufferFull2 ;
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reg rxRun2 ;
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reg rxRun2 ;
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reg txRun2 ;
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reg txRun2 ;
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always @(posedge clk) begin
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always @(posedge clk) begin
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//bufferFull <= statusOut[0];
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//bufferFull <= statusOut[0];
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rxRun <= statusOut[5];
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rxRun <= statusOut[5];
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txRun <= statusOut[7];
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txRun <= statusOut[7];
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//bufferFull2 <= statusOut2[0];
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//bufferFull2 <= statusOut2[0];
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rxRun2 <= statusOut2[5];
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rxRun2 <= statusOut2[5];
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txRun2 <= statusOut2[7];
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txRun2 <= statusOut2[7];
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end
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end
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task sendByte;
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task sendByte;
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input [7:0] data;
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input [7:0] data;
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begin
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begin
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wait(bufferFull==1'b0);
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wait(bufferFull==1'b0);
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dataIn=data;
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dataIn=data;
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nWeDataIn=0;
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nWeDataIn=0;
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@(posedge clk);
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@(posedge clk);
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dataIn=8'hxx;
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dataIn=8'hxx;
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nWeDataIn=1;
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nWeDataIn=1;
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@(posedge clk);
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@(posedge clk);
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end
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end
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endtask
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endtask
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task sendByte2;
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task sendByte2;
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input [7:0] data;
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input [7:0] data;
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begin
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begin
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wait(bufferFull2==1'b0);
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wait(bufferFull2==1'b0);
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dataIn2=data;
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dataIn2=data;
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nWeDataIn2=0;
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nWeDataIn2=0;
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@(posedge clk);
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@(posedge clk);
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dataIn2=8'hxx;
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dataIn2=8'hxx;
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nWeDataIn2=1;
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nWeDataIn2=1;
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@(posedge clk);
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@(posedge clk);
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end
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end
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endtask
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endtask
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task receiveByte;
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task receiveByte;
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input [7:0] data;
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input [7:0] data;
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begin
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begin
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wait(txPending==1'b0);//wait start of last tx if any
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wait(txPending==1'b0);//wait start of last tx if any
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wait(txRun==1'b0);//wait end of previous transmission if any
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wait(txRun==1'b0);//wait end of previous transmission if any
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wait(bufferFull==1'b1);//wait reception of a byte
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wait(bufferFull==1'b1);//wait reception of a byte
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@(posedge clk);
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@(posedge clk);
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nCsDataOut=0;
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nCsDataOut=0;
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@(posedge clk);
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@(posedge clk);
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nCsDataOut=1;
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nCsDataOut=1;
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if(data!=dataOut) begin
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if(data!=dataOut) begin
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tbErrorCnt=tbErrorCnt+1;
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tbErrorCnt=tbErrorCnt+1;
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$display("ERROR %d: uart1 received %x instead of %x",tbErrorCnt, dataOut, data);
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$display("ERROR %d: uart1 received %x instead of %x",tbErrorCnt, dataOut, data);
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end
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end
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@(posedge clk);
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@(posedge clk);
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end
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end
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endtask
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endtask
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task receiveByte2;
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task receiveByte2;
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input [7:0] data;
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input [7:0] data;
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begin
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begin
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wait(txPending2==1'b0);//wait start of last tx if any
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wait(txPending2==1'b0);//wait start of last tx if any
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wait(txRun2==1'b0);//wait end of previous transmission if any
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wait(txRun2==1'b0);//wait end of previous transmission if any
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wait(bufferFull2==1'b1);//wait reception of a byte
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wait(bufferFull2==1'b1);//wait reception of a byte
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@(posedge clk);
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@(posedge clk);
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nCsDataOut2=0;
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nCsDataOut2=0;
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@(posedge clk);
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@(posedge clk);
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nCsDataOut2=1;
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nCsDataOut2=1;
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if(data!=dataOut2) begin
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if(data!=dataOut2) begin
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tbErrorCnt=tbErrorCnt+1;
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tbErrorCnt=tbErrorCnt+1;
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$display("ERROR %d: uart2 received %x instead of %x (time=%d)",tbErrorCnt, dataOut2, data,$time);
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$display("ERROR %d: uart2 received %x instead of %x (time=%d)",tbErrorCnt, dataOut2, data,$time);
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end else
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end else
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$display("INFO: uart2 received %x (time=%d)",dataOut2,$time);
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$display("INFO: uart2 received %x (time=%d)",dataOut2,$time);
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@(posedge clk);
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@(posedge clk);
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end
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end
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endtask
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endtask
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integer tbSequenceDone;
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integer tbSequenceDone;
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integer tbSequenceDone2;
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integer tbSequenceDone2;
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initial begin
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initial begin
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// Initialize Inputs
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// Initialize Inputs
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nReset = 0;
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nReset = 0;
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clk = 0;
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clk = 0;
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dataIn = 0;
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dataIn = 0;
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clkPerCycle = 0;
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clkPerCycle = 0;
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nWeDataIn = 1;
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nWeDataIn = 1;
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nCsDataOut = 1;
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nCsDataOut = 1;
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nCsStatusOut = 1;
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nCsStatusOut = 1;
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nWeDataIn2 = 1;
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nWeDataIn2 = 1;
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nCsDataOut2 = 1;
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nCsDataOut2 = 1;
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nCsStatusOut2 = 1;
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nCsStatusOut2 = 1;
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tbErrorCnt=0;
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tbErrorCnt=0;
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tbSequenceDone=0;
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tbSequenceDone=0;
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tbSequenceDone2=0;
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tbSequenceDone2=0;
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// Wait 100 ns for global reset to finish
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// Wait 100 ns for global reset to finish
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#(CLK_PERIOD*10);
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#(CLK_PERIOD*10);
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#(CLK_PERIOD/2);
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#(CLK_PERIOD/2);
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nReset = 1;
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nReset = 1;
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// Add stimulus here
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// Add stimulus here
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@(posedge clk);
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@(posedge clk);
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dataIn=8'h3B;
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dataIn=8'h3B;
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nWeDataIn=0;
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nWeDataIn=0;
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@(posedge clk);
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@(posedge clk);
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dataIn=8'h00;
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dataIn=8'h00;
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nWeDataIn=1;
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nWeDataIn=1;
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@(posedge clk);
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@(posedge clk);
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if(bufferFull==1'b0) begin
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if(bufferFull==1'b0) begin
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tbErrorCnt=tbErrorCnt+1;
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tbErrorCnt=tbErrorCnt+1;
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$display("ERROR %d: bufferFull==1'b0",tbErrorCnt);
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$display("ERROR %d: bufferFull==1'b0",tbErrorCnt);
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end
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end
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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if(bufferFull==1'b1) begin
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if(bufferFull==1'b1) begin
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tbErrorCnt=tbErrorCnt+1;
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tbErrorCnt=tbErrorCnt+1;
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$display("ERROR %d: bufferFull==1'b1",tbErrorCnt);
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$display("ERROR %d: bufferFull==1'b1",tbErrorCnt);
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end
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end
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//sendByte(8'h3B);
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//sendByte(8'h3B);
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sendByte(8'h97);
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sendByte(8'h97);
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sendByte(8'h12);
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sendByte(8'h12);
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sendByte(8'h34);
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sendByte(8'h34);
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receiveByte(8'h55);
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receiveByte(8'h55);
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sendByte(8'h56);
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sendByte(8'h56);
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sendByte(8'h78);
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sendByte(8'h78);
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tbSequenceDone=1;
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tbSequenceDone=1;
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end
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end
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initial begin
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initial begin
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receiveByte2(8'h3B);
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receiveByte2(8'h3B);
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receiveByte2(8'h97);
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receiveByte2(8'h97);
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receiveByte2(8'h12);
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receiveByte2(8'h12);
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receiveByte2(8'h34);
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receiveByte2(8'h34);
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sendByte2(8'h55);
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sendByte2(8'h55);
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receiveByte2(8'h56);
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receiveByte2(8'h56);
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receiveByte2(8'h78);
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receiveByte2(8'h78);
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tbSequenceDone2=1;
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tbSequenceDone2=1;
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end
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end
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initial begin
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initial begin
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wait(tbSequenceDone & tbSequenceDone2);
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wait(tbSequenceDone & tbSequenceDone2);
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if(tbErrorCnt)
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if(tbErrorCnt)
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$display("INFO: Test FAILED (%d errors)", tbErrorCnt);
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$display("INFO: Test FAILED (%d errors)", tbErrorCnt);
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else
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else
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$display("INFO: Test PASSED");
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$display("INFO: Test PASSED");
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#10;
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#10;
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$finish;
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$finish;
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end
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end
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initial begin
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initial begin
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// timeout
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// timeout
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#10000;
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#10000;
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tbErrorCnt=tbErrorCnt+1;
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tbErrorCnt=tbErrorCnt+1;
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$display("ERROR: timeout expired");
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$display("ERROR: timeout expired");
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#10;
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#10;
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$finish;
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$finish;
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end
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end
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always
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always
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#(CLK_PERIOD/2) clk = ! clk;
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#(CLK_PERIOD/2) clk = ! clk;
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endmodule
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endmodule
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