`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`default_nettype none
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`default_nettype none
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module TsAnalyzer(
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module TsAnalyzer(
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input wire nReset,
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input wire nReset,
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input wire isoReset,
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input wire isoReset,
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input wire isoClk,
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input wire isoClk,
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input wire isoVdd,
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input wire isoVdd,
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input wire isoSio,
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input wire isoSio,
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input wire endOfRx,
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input wire endOfRx,
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input wire [7:0] rxData,//assumed to be sent lsb first, high level coding logical 1.
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input wire [7:0] rxData,//assumed to be sent lsb first, high level coding logical 1.
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output wire isActivated,
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output wire isActivated,
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output wire tsReceived,
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output wire tsReceived,
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output wire tsError,
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output wire tsError,
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output wire atrIsEarly,//high if TS received before 400 cycles after reset release
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output wire atrIsEarly,//high if TS received before 400 cycles after reset release
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output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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output wire useIndirectConvention
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output wire useIndirectConvention
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);
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);
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reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
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reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
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reg [16:0] resetCnt;
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reg [16:0] resetCnt;
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reg waitTs;
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reg waitTs;
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assign tsReceived = ~waitTs;
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assign tsReceived = ~waitTs;
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reg [7:0] ts;
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reg [7:0] ts;
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assign atrIsEarly = ~waitTs & (resetCnt<(16'h100+16'd400));
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assign atrIsEarly = ~waitTs & (resetCnt<(16'h100+16'd400));
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assign atrIsLate = resetCnt>(16'h100+16'd40000);
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assign atrIsLate = resetCnt>(16'h100+16'd40000);
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assign useIndirectConvention = ~waitTs & (ts==8'hFC);//FC is 3F written LSB first
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assign useIndirectConvention = ~waitTs & (ts==8'hFC);//FC is 3F written LSB first
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assign tsError = ~waitTs & (ts!=8'h3B) & ~useIndirectConvention;
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assign tsError = ~waitTs & (ts!=8'h3B) & ~useIndirectConvention;
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assign isActivated = isoReset & isoVdd;
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assign isActivated = isoReset & isoVdd;
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always @(posedge isoClk, negedge nReset) begin
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always @(posedge isoClk, negedge nReset) begin
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if(~nReset) begin
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if(~nReset) begin
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resetCnt<=16'b0;
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resetCnt<=16'b0;
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waitTs<=1'b1;
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waitTs<=1'b1;
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end else if(isActivated) begin
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end else if(isActivated) begin
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if(waitTs) begin
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if(waitTs) begin
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if(endOfRx) begin
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if(endOfRx) begin
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waitTs<=1'b0;
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waitTs<=1'b0;
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ts<=rxData;
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ts<=rxData;
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end
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end
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resetCnt<=resetCnt+1;
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resetCnt<=resetCnt+1;
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end
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end
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end else begin
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end else begin
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if(isoVdd & isoReset) begin
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if(isoVdd & isoReset) begin
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resetCnt<=resetCnt + 1;
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resetCnt<=resetCnt + 1;
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end else begin
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end else begin
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resetCnt<=16'b0;
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resetCnt<=16'b0;
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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