/*
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/*
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Author: Sebastien Riou (acapola)
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Author: Sebastien Riou (acapola)
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Creation date: 22:22:43 01/10/2011
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Creation date: 22:22:43 01/10/2011
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$LastChangedDate: 2011-02-18 15:23:07 +0100 (Fri, 18 Feb 2011) $
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$LastChangedDate: 2011-03-07 14:17:52 +0100 (Mon, 07 Mar 2011) $
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$LastChangedBy: acapola $
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$LastChangedBy: acapola $
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$LastChangedRevision: 17 $
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$LastChangedRevision: 18 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/tsAnalyzer.v $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/tsAnalyzer.v $
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This file is under the BSD licence:
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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Copyright (c) 2011, Sebastien Riou
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All rights reserved.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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`default_nettype none
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`default_nettype none
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module TsAnalyzer(
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module TsAnalyzer(
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input wire nReset,
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input wire nReset,
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input wire isoReset,
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input wire isoReset,
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input wire isoClk,
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input wire isoClk,
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input wire isoVdd,
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input wire isoVdd,
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input wire isoSio,
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input wire isoSio,
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input wire endOfRx,
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input wire endOfRx,
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input wire [7:0] rxData,//assumed to be sent lsb first, high level coding logical 1.
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input wire [7:0] rxData,//assumed to be sent lsb first, high level coding logical 1.
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output wire isActivated,
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output wire isActivated,
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output wire tsReceived,
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output wire tsReceived,
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output wire tsError,
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output wire tsError,
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output wire atrIsEarly,//high if TS received before 400 cycles after reset release
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output wire atrIsEarly,//high if TS received before 400 cycles after reset release
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output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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output wire useIndirectConvention,
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output wire useIndirectConvention,
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output reg [7:0] ts
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output reg [7:0] ts
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);
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);
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reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
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reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
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reg [16:0] resetCnt;
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reg [16:0] resetCnt;
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reg waitTs;
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reg waitTs;
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assign tsReceived = ~waitTs;
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assign tsReceived = ~waitTs;
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assign atrIsEarly = ~waitTs & (resetCnt<(16'h100+16'd400));
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assign atrIsEarly = ~waitTs & (resetCnt<(16'h100+16'd400));
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assign atrIsLate = resetCnt>(16'h100+16'd40000);
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assign atrIsLate = resetCnt>(16'h100+16'd40000);
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assign useIndirectConvention = ~waitTs & (ts==8'h3F);
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assign useIndirectConvention = ~waitTs & (ts==8'h3F);
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assign tsError = ~waitTs & (ts!=8'h3B) & (ts!=8'h3F);
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assign tsError = ~waitTs & (ts!=8'h3B) & (ts!=8'h3F);
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assign isActivated = isoReset & isoVdd;
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assign isActivated = isoReset & isoVdd;
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wire fsm_nReset=nReset & isoReset & isoVdd;
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wire fsm_nReset=nReset & isoReset & isoVdd;
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always @(posedge isoClk, negedge fsm_nReset) begin
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always @(posedge isoClk, negedge fsm_nReset) begin
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if(~fsm_nReset) begin
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if(~fsm_nReset) begin
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resetCnt<=16'b0;
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resetCnt<=16'b0;
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waitTs<=1'b1;
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waitTs<=1'b1;
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end else if(isActivated) begin
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end else if(isActivated) begin
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if(waitTs) begin
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if(waitTs) begin
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if(endOfRx) begin
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if(endOfRx) begin
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waitTs<=1'b0;
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waitTs<=1'b0;
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case(rxData)
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case(rxData)
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8'h3B: ts<=rxData;
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8'h3B: ts<=rxData;
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8'h03: ts<=8'h3F;//03 is 3F written LSB first and complemented
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8'h03: ts<=8'h3F;//03 is 3F written LSB first and complemented
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default: ts<=rxData;
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default: ts<=rxData;
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endcase
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endcase
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end
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end
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resetCnt<=resetCnt+1;
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resetCnt<=resetCnt+1'b1;
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end
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end
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end else begin
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end else begin
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//if(isoVdd & isoReset) begin
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//if(isoVdd & isoReset) begin
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resetCnt<=resetCnt + 1;
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resetCnt<=resetCnt + 1'b1;
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//end else begin
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//end else begin
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// resetCnt<=16'b0;
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// resetCnt<=16'b0;
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//end
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//end
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end
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end
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end
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end
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endmodule
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endmodule
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`default_nettype wire
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`default_nettype wire
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