-- Author : Julian Andres Guarin Reyes.
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-- Author : Julian Andres Guarin Reyes.
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-- Project : JART, Just Another Ray Tracer.
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-- Project : JART, Just Another Ray Tracer.
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-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
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-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
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-- This code was entirely written by Julian Andres Guarin Reyes.
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-- This code was entirely written by Julian Andres Guarin Reyes.
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-- The following code is licensed under GNU Public License
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-- The following code is licensed under GNU Public License
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-- http://www.gnu.org/licenses/gpl-3.0.txt.
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-- http://www.gnu.org/licenses/gpl-3.0.txt.
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-- This file is part of JART (Just Another Ray Tracer).
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-- This file is part of JART (Just Another Ray Tracer).
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-- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
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-- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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-- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
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-- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>.
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-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>.
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-- A single dot product cell.
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-- A single dot product cell.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.powerGrid.all;
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use work.powerGrid.all;
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entity dotCell is
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entity dotCell is
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generic ( RV : string := "yes";
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generic ( RV : string := "yes";
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W0 : integer := 18; -- Actual Level Width
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W0 : integer := 18; -- Actual Level Width
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W1 : integer := 32); -- Next Level Width
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W1 : integer := 32); -- Next Level Width
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port ( clk : in std_logic;
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port ( clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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-- Object control.
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-- Object control.
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nxtSphere : in std_logic; -- This signal controls when the sphere center goes to the next row.
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nxtSphere : in std_logic; -- This signal controls when the sphere center goes to the next row.
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nxtRay : in std_logic; -- This signal controls when the ray goes to the next column.
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nxtRay : in std_logic; -- This signal controls when the ray goes to the next column.
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-- First Side.
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-- First Side.
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vxInput : in std_logic_vector(W0-1 downto 0);
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vxInput : in std_logic_vector(W0-1 downto 0);
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vyInput : in std_logic_vector(W0-1 downto 0);
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vyInput : in std_logic_vector(W0-1 downto 0);
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vzInput : in std_logic_vector(W0-1 downto 0);
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vzInput : in std_logic_vector(W0-1 downto 0);
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-- Second Side (Opposite to the first one)
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-- Second Side (Opposite to the first one)
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vxOutput : out std_logic_vector(W0-1 downto 0);
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vxOutput : out std_logic_vector(W0-1 downto 0);
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vyOutput : out std_logic_vector(W0-1 downto 0);
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vyOutput : out std_logic_vector(W0-1 downto 0);
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vzOutput : out std_logic_vector(W0-1 downto 0);
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vzOutput : out std_logic_vector(W0-1 downto 0);
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-- Third Side (Perpendicular to the first and second ones)
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-- Third Side (Perpendicular to the first and second ones)
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dxInput : in std_logic_vector(W0-1 downto 0);
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dxInput : in std_logic_vector(W0-1 downto 0);
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dyInput : in std_logic_vector(W0-1 downto 0);
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dyInput : in std_logic_vector(W0-1 downto 0);
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dzInput : in std_logic_vector(W0-1 downto 0);
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dzInput : in std_logic_vector(W0-1 downto 0);
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--Fourth Side (Opposite to the third one)
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--Fourth Side (Opposite to the third one)
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dxOutput : out std_logic_vector(W0-1 downto 0);
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dxOutput : out std_logic_vector(W0-1 downto 0);
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dyOutput : out std_logic_vector(W0-1 downto 0);
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dyOutput : out std_logic_vector(W0-1 downto 0);
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dzOutput : out std_logic_vector(W0-1 downto 0);
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dzOutput : out std_logic_vector(W0-1 downto 0);
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--Fifth Side (Going to the floor right upstairs!)
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--Fifth Side (Going to the floor right upstairs!)
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vdOutput : out std_logic_vector(W1-1 downto 0) -- Dot product.
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vdOutput : out std_logic_vector(W1-1 downto 0) -- Dot product.
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);
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);
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end entity;
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end entity;
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architecture rtl of dotCell is
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architecture rtl of dotCell is
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signal s36vd : std_logic_vector (2*W0-1 downto 0);
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signal s36vd : std_logic_vector (2*W0-1 downto 0);
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signal s36m0 : std_logic_vector (2*W0-1 downto 0);
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signal s36m0 : std_logic_vector (2*W0-1 downto 0);
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signal s36m1 : std_logic_vector (2*W0-1 downto 0);
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signal s36m1 : std_logic_vector (2*W0-1 downto 0);
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signal s36m2 : std_logic_vector (2*W0-1 downto 0);
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signal s36m2 : std_logic_vector (2*W0-1 downto 0);
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signal pAdd : std_logic_vector (W0-1 downto 0);
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signal pAdd : std_logic_vector (W0-1 downto 0);
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begin
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begin
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-- The Dotprod Machine
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-- The Dotprod Machine
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-- 18x18 1 stage pipe Multipliers.
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-- 18x18 1 stage pipe Multipliers.
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m0 : p1m18 port map (
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m0 : p1m18 port map (
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aclr => not(rst),
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aclr => not(rst),
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clken => nxtRay,
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clken => nxtRay,
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clock => clk,
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clock => clk,
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dataa => vxInput,
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dataa => vxInput,
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datab => dxInput,
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datab => dxInput,
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result => s36m0
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result => s36m0
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);
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);
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m1 : p1m18 port map (
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m1 : p1m18 port map (
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aclr => not(rst),
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aclr => not(rst),
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clken => nxtRay,
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clken => nxtRay,
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clock => clk,
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clock => clk,
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dataa => vyInput,
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dataa => vyInput,
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datab => dyInput,
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datab => dyInput,
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result => s36m1
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result => s36m1
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);
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);
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m2 : p1m18 port map (
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m2 : p1m18 port map (
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aclr => not(rst),
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aclr => not(rst),
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clken => nxtRay,
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clken => nxtRay,
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clock => clk,
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clock => clk,
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dataa => vzInput,
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dataa => vzInput,
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datab => dzInput,
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datab => dzInput,
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result => s36m2
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result => s36m2
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);
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);
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-- 36 bits a+b+c 1 stage pipe Adder.
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-- 36 bits a+b+c 1 stage pipe Adder.
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a0 : p1ax port map (
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a0 : p1ax port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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enable => nxtRay,
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enable => nxtRay,
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dataa => s36m0,
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dataa => s36m0,
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datab => s36m1,
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datab => s36m1,
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datac => s36m2,
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datac => s36m2,
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result => s36vd
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result => s36vd
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);
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);
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-- Truncate the less signifcative 4 bits 35 downto 4.
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-- Truncate the less signifcative 4 bits 35 downto 4.
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vdOutput <= s36vd (2*W0-1 downto 2*W0-W1);
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vdOutput <= s36vd (2*W0-1 downto 2*W0-W1);
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-- Ray PipeLine
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-- Ray PipeLine
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rayPipeStage : process (clk,rst,nxtRay)
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rayPipeStage : process (clk,rst,nxtRay)
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begin
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begin
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if rst = '0' then
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if rst = '0' then
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-- There is no ray load yet.
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-- There is no ray load yet.
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dxOutput <= (others => '0');
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dxOutput <= (others => '0');
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dyOutput <= (others => '0');
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dyOutput <= (others => '0');
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dzOutput <= (others => '0');
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dzOutput <= (others => '0');
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elsif rising_edge (clk) and nxtRay='1' then
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elsif rising_edge (clk) and nxtRay='1' then
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-- Set
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-- Set
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dxOutput <= dxInput;
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dxOutput <= dxInput;
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dyOutput <= dyInput;
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dyOutput <= dyInput;
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dzOutput <= dzInput;
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dzOutput <= dzInput;
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end if;
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end if;
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end process;
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end process;
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-- Sphere Pipe Line
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-- Sphere Pipe Line
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registerV : if RV="yes" generate
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registerV : if RV="yes" generate
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spherePipeStage : process (clk,rst,nxtSphere)
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spherePipeStage : process (clk,rst,nxtSphere)
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begin
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begin
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if rst = '0' then
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if rst = '0' then
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-- There is no object center yet.
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-- There is no object center yet.
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vxOutput <= (others => '0');
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vxOutput <= (others => '0');
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vyOutput <= (others => '0');
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vyOutput <= (others => '0');
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vzOutput <= (others => '0');
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vzOutput <= (others => '0');
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elsif rising_edge (clk) and nxtSphere ='1' then
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elsif rising_edge (clk) and nxtSphere ='1' then
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-- Shift sphere to the next row.
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-- Shift sphere to the next row.
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vxOutput <= vxInput;
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vxOutput <= vxInput;
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vyOutput <= vyInput;
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vyOutput <= vyInput;
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vzOutput <= vzInput;
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vzOutput <= vzInput;
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end if;
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end if;
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end process;
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end process;
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end generate;
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end generate;
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end rtl;
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end rtl;
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