library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_signed.all;
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use ieee.std_logic_signed.all;
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entity p1ax is
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entity p1ax is
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generic ( W : integer := 36 );
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generic ( W : integer := 36 );
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port (
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port (
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clk,rst,enable : in std_logic; -- The usual control signals.
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clk,rst,enable : in std_logic; -- The usual control signals.
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dataa,datab,datac : in std_logic_vector (W-1 downto 0);
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dataa,datab,datac : in std_logic_vector (W-1 downto 0);
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result : out std_logic_vector (W-1 downto 0)
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result : out std_logic_vector (W-1 downto 0)
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);
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);
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end entity;
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end entity;
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architecture rtl of p1ax is
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architecture rtl of p1ax is
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signal sdresult0 : std_logic_vector (W-1 downto 0);
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signal sdresult0 : std_logic_vector (W-1 downto 0);
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--signal sdresult1 : std_logic_vector (W-1 downto 0);
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--signal sdresult1 : std_logic_vector (W-1 downto 0);
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begin
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begin
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sdresult0 <= dataa+datab+datac;
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sdresult0 <= dataa+datab+datac;
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--sdresult1 <= sdresult0+datac;
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--sdresult1 <= sdresult0+datac;
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process (clk,rst,enable)
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process (clk,rst,enable)
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begin
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begin
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if rst = '0' then
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if rst = '0' then
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result <= (others =>'0');
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result <= (others =>'0');
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elsif rising_edge(clk) and enable ='1' then
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elsif rising_edge(clk) and enable ='1' then
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result <= sdresult0;
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result <= sdresult0;
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end if;
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end if;
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end process;
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end process;
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end rtl;
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end rtl;
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