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-- Author : Julian Andres Guarin Reyes.
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-- Project : JART, Just Another Ray Tracer.
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-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
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-- This code was entirely written by Julian Andres Guarin Reyes.
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-- The following code is licensed under GNU Public License
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-- http://www.gnu.org/licenses/gpl-3.0.txt.
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-- This file is part of JART (Just Another Ray Tracer).
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-- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>.
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-- A 1 clock x 4 stage pipe square root.
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-- A 1 clock x 4 stage pipe square root.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use work.powerGrid.all;
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use work.powerGrid.all;
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entity sqrt is
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entity sqrt is
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generic (
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generic (
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W2 : integer := 64
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W2 : integer := 64
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);
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);
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port
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port
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(
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(
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clk,rst,ena : in std_logic;
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clk,rst,ena : in std_logic;
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radical : in std_logic_vector (W2-1 downto 0);
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radical : in std_logic_vector (W2-1 downto 0);
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root : out std_logic_vector ((W2/2)-1 downto 0)
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root : out std_logic_vector ((W2/2)-1 downto 0)
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);
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);
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end entity;
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end entity;
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architecture rtl of sqrt is
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architecture rtl of sqrt is
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constant WP : integer:= W2/2;
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constant WP : integer:= W2/2;
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constant WP_2 : integer:= WP/2;
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constant WP_2 : integer:= WP/2;
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signal sa0,sb0,sx0,sy0,sb0_1 : std_logic_vector (WP-1 downto 0);
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signal sa0,sb0,sx0,sy0,sb0_1 : std_logic_vector (WP-1 downto 0);
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signal sa1,sb1,sx1,sy1,sb1_1,muxs1 : std_logic_vector (WP-1 downto 0);
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signal sa1,sb1,sx1,sy1,sb1_1,muxs1 : std_logic_vector (WP-1 downto 0);
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signal sa2,sb2,sx2,sy2 : std_logic_vector (WP-1 downto 0);
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signal sa2,sb2,sx2,sy2 : std_logic_vector (WP-1 downto 0);
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signal localenc1 : integer range 0 to WP-1;
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signal localenc1 : integer range 0 to WP-1;
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signal localenc2 : integer range 0 to WP-1;
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signal localenc2 : integer range 0 to WP-1;
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signal sho : std_logic;
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signal sho : std_logic;
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signal a,b,x,y : std_logic_vector ((W2/2)-1 downto 0);
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signal a,b,x,y : std_logic_vector ((W2/2)-1 downto 0);
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signal decoder : integer range 0 to (W2/2)-1;
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signal decoder : integer range 0 to (W2/2)-1;
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signal ab,xy : std_logic_vector (W2-1 downto 0);
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signal ab,xy : std_logic_vector (W2-1 downto 0);
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begin
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begin
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-- Logic function signals ...... if some day there's a paper of how this logic circuit works, it will be easier to comprehend this block of code
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-- Logic function signals ...... if some day there's a paper of how this logic circuit works, it will be easier to comprehend this block of code
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sb0_1<=sa0(WP-2 downto 0) & '0';
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sb0_1<=sa0(WP-2 downto 0) & '0';
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signalization : for i in 0 to WP-1 generate
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signalization : for i in 0 to WP-1 generate
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-- Stage 0. Functions for A,B,X and preliminar Y.
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-- Stage 0. Functions for A,B,X and preliminar Y.
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sb0(i)<=radical(i*2);
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sb0(i)<=radical(i*2);
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sa0(i)<=radical(i*2+1);
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sa0(i)<=radical(i*2+1);
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sx0(i)<=sb0(i) or sa0(i);
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sx0(i)<=sb0(i) or sa0(i);
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sy0(i)<=sb0(i) and sa0(i);
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sy0(i)<=sb0(i) and sa0(i);
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-- Stage 1 : Function for signal Y.
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-- Stage 1 : Function for signal Y.
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muxs1(i) <= sy1(i) or (not(sx1(i)) and sb1_1(i));
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muxs1(i) <= sy1(i) or (not(sx1(i)) and sb1_1(i));
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-- Stage 3 :
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-- Stage 3 :
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ab(i*2) <= b(i);
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ab(i*2) <= b(i);
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ab(i*2+1) <= a(i);
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ab(i*2+1) <= a(i);
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xy(i*2) <= y(i);
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xy(i*2) <= y(i);
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xy(i*2+1) <= x(i);
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xy(i*2+1) <= x(i);
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end generate signalization;
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end generate signalization;
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stages: process (rst,clk,ena,sx0,sx1,localenc2)
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stages: process (rst,clk,ena,sx0,sx1,localenc2)
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variable localenc0 : integer range 0 to WP-1;
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variable localenc0 : integer range 0 to WP-1;
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begin
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begin
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-- Highest signifcant pair enconder : look for the bit pair with the most significant bit.
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-- Highest signifcant pair enconder : look for the bit pair with the most significant bit.
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localenc0 := WP-1;
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localenc0 := WP-1;
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stg0henc: while localenc0>0 loop
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stg0henc: while localenc0>0 loop
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exit when (sx0(localenc0)='1');
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exit when (sx0(localenc0)='1');
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localenc0:=localenc0-1;
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localenc0:=localenc0-1;
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end loop;
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end loop;
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-- Clocking process;
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-- Clocking process;
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if rst='0' then
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if rst='0' then
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-- Stage 1
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-- Stage 1
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sa1<=(others => '0');
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sa1<=(others => '0');
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sb1<=(others => '0');
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sb1<=(others => '0');
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sx1<=(others => '0');
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sx1<=(others => '0');
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sy1<=(others => '0');
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sy1<=(others => '0');
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sb1_1<=(others => '0');
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sb1_1<=(others => '0');
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-- Stage 2
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-- Stage 2
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sx2<=(others => '0');
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sx2<=(others => '0');
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sa2<=(others => '0');
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sa2<=(others => '0');
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sb2<=(others => '0');
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sb2<=(others => '0');
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sy2<=(others => '0');
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sy2<=(others => '0');
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--Stage 3
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--Stage 3
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x<=(others => '0');
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x<=(others => '0');
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y<=(others => '0');
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y<=(others => '0');
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a<=(others => '0');
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a<=(others => '0');
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b<=(others => '0');
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b<=(others => '0');
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--Stage 4
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--Stage 4
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root <= (others=>'0');
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root <= (others=>'0');
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elsif rising_edge(clk) and ena='1' then
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elsif rising_edge(clk) and ena='1' then
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-- Stage01
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-- Stage01
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sa1<=sa0;
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sa1<=sa0;
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sb1<=sb0;
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sb1<=sb0;
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sx1<=sx0;
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sx1<=sx0;
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sy1<=sy0;
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sy1<=sy0;
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sb1_1<=sb0_1;
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sb1_1<=sb0_1;
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localenc1<=localenc0;
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localenc1<=localenc0;
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-- Stage12
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-- Stage12
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sx2<=sx1;
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sx2<=sx1;
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sa2<=sa1;
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sa2<=sa1;
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sb2<=sb1;
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sb2<=sb1;
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sy2<= muxs1;
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sy2<= muxs1;
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localenc2<=localenc1;
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localenc2<=localenc1;
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-- Stage 23 Shift 1 bit to right if the high bit in the highest significant pair is set.
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-- Stage 23 Shift 1 bit to right if the high bit in the highest significant pair is set.
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if sa2(localenc2)='1' then
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if sa2(localenc2)='1' then
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-- Shift Right
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-- Shift Right
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a <= '0' & sb2(WP-1 downto 1);
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a <= '0' & sb2(WP-1 downto 1);
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b <= sa2;
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b <= sa2;
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x <= '0' & sy2(WP-1 downto 1);
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x <= '0' & sy2(WP-1 downto 1);
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y <= sx2;
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y <= sx2;
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else
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else
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-- Leave me alone
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-- Leave me alone
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x <= sx2;
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x <= sx2;
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y <= sy2;
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y <= sy2;
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a <= sa2;
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a <= sa2;
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b <= sb2;
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b <= sb2;
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end if;
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end if;
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decoder<=localenc2;
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decoder<=localenc2;
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sho<=sa2(localenc2);
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sho<=sa2(localenc2);
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-- stage34
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-- stage34
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for i in 0 to WP-1 loop
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for i in 0 to WP-1 loop
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if i>decoder then
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if i>decoder then
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root(i)<='0';
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root(i)<='0';
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elsif decoder-i>2 then
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elsif decoder-i>2 then
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root(i)<=ab(decoder+i+1);
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root(i)<=ab(decoder+i+1);
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elsif decoder-i=2 then
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elsif decoder-i=2 then
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root(i)<=(ab(decoder+i+1) and not(sho)) or (xy(decoder+i+1) and sho);
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root(i)<=(ab(decoder+i+1) and not(sho)) or (xy(decoder+i+1) and sho);
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else
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else
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root(i)<=xy(decoder+i+1);
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root(i)<=xy(decoder+i+1);
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end if;
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end if;
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end loop;
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end loop;
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end if;
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end if;
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end process stages;
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end process stages;
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end rtl;
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end rtl;
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