-- Author : Julian Andres Guarin Reyes.
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-- Author : Julian Andres Guarin Reyes.
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-- Project : JART, Just Another Ray Tracer.
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-- Project : JART, Just Another Ray Tracer.
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-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
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-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
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-- This code was entirely written by Julian Andres Guarin Reyes.
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-- This code was entirely written by Julian Andres Guarin Reyes.
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-- The following code is licensed under GNU Public License
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-- The following code is licensed under GNU Public License
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-- http://www.gnu.org/licenses/gpl-3.0.txt.
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-- http://www.gnu.org/licenses/gpl-3.0.txt.
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-- This file is part of JART (Just Another Ray Tracer).
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-- This file is part of JART (Just Another Ray Tracer).
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-- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
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-- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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-- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
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-- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>.
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-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity uart is
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entity uart is
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port(
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port(
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rst : in std_logic; -- reset control signal
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rst : in std_logic; -- reset control signal
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clk : in std_logic; -- 100 MHz on PLL
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clk : in std_logic; -- 100 MHz on PLL
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-- Reception channel
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-- Reception channel
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Rx : in std_logic; -- Linea de entrada RS232
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Rx : in std_logic; -- Linea de entrada RS232
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RxDataOut : out std_logic_vector(7 downto 0); -- Buffer de salida
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RxDataOut : out std_logic_vector(7 downto 0); -- Buffer de salida
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RxRdy : out std_logic; -- Bandera para indicar que el dato esta listo
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RxRdy : out std_logic; -- Bandera para indicar que el dato esta listo
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-- Transmition channel
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-- Transmition channel
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Tx : out std_logic; -- Linea de salida RS232
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Tx : out std_logic; -- Linea de salida RS232
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TxDataIn : in std_logic_vector(7 downto 0); -- Buffer de entrada
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TxDataIn : in std_logic_vector(7 downto 0); -- Buffer de entrada
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TxLoad : in std_logic; -- Señal de carga
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TxLoad : in std_logic; -- Señal de carga
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TxBusy : out std_logic -- Bandera de Canal ocupado
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TxBusy : out std_logic -- Bandera de Canal ocupado
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);
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);
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end entity;
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end entity;
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architecture rtl of uart is
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architecture rtl of uart is
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Ticks
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-- Ticks
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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constant TBIT : integer := 434/4; -- 15 1 bit Divide By four in order to obtain 460800 bps at 50 MHZ, by 2 for 230400, by 1 for 115200 bps
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constant TBIT : integer := 434/4; -- 15 1 bit Divide By four in order to obtain 460800 bps at 50 MHZ, by 2 for 230400, by 1 for 115200 bps
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constant THALF_BIT : integer := 217/4; -- 7 1/2 bit Divide By four in order to obtain 460800 bps at 50 MHZ, by 2 for 230400, by 1 for 115200 bps
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constant THALF_BIT : integer := 217/4; -- 7 1/2 bit Divide By four in order to obtain 460800 bps at 50 MHZ, by 2 for 230400, by 1 for 115200 bps
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Maquinas de Estado
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-- Maquinas de Estado
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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type tTxStateMachine is (WAITING_LOAD_TX,SET_STARTBIT_TX,SET_NBIT_TX,FINISH_TX);
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type tTxStateMachine is (WAITING_LOAD_TX,SET_STARTBIT_TX,SET_NBIT_TX,FINISH_TX);
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type tRxStateMachine is (WAIT_START_BIT,HOLD_STARTBIT_RX,WAIT_FOR_NEW_BIT_RX,SAMPLE_BIT_RX,SAMPLE_STOPBIT_RX);--,RX_OVF,DEBUGGING_RX);
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type tRxStateMachine is (WAIT_START_BIT,HOLD_STARTBIT_RX,WAIT_FOR_NEW_BIT_RX,SAMPLE_BIT_RX,SAMPLE_STOPBIT_RX);--,RX_OVF,DEBUGGING_RX);
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signal sTxState : tTxStateMachine;
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signal sTxState : tTxStateMachine;
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signal sRxState : tRxStateMachine;
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signal sRxState : tRxStateMachine;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Baud Rate Signals : Bit 16th bit16, Bit half bit2, Entire Bit bit1.
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-- Baud Rate Signals : Bit 16th bit16, Bit half bit2, Entire Bit bit1.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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signal bit2 : std_logic; -- 1/2 BAUDIO
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signal bit2 : std_logic; -- 1/2 BAUDIO
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signal bit1 : std_logic; -- 1 BAUDIO
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signal bit1 : std_logic; -- 1 BAUDIO
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Registros de Transmision
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-- Registros de Transmision
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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signal sTxDataInReg : std_logic_vector(7 downto 0); -- Registro de precarga de salida
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signal sTxDataInReg : std_logic_vector(7 downto 0); -- Registro de precarga de salida
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signal sShiftTxData : std_logic_vector(9 downto 0); -- Registro de corrimiento de salida
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signal sShiftTxData : std_logic_vector(9 downto 0); -- Registro de corrimiento de salida
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Registros de Recepcion
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-- Registros de Recepcion
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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signal sShiftRxData : std_logic_vector(7 downto 0); -- Registro de corrimiento de llegada.
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signal sShiftRxData : std_logic_vector(7 downto 0); -- Registro de corrimiento de llegada.
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signal sSyncRxCounter : std_logic; -- Señal de sincronizacion para el contador de medio bit.
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signal sSyncRxCounter : std_logic; -- Señal de sincronizacion para el contador de medio bit.
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signal sEnableTxCounter : std_logic; -- Señal de sincronizacion para conteo de un bit entero en la transmision.
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signal sEnableTxCounter : std_logic; -- Señal de sincronizacion para conteo de un bit entero en la transmision.
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signal sRx0, sRx1 : std_logic; -- Señal Rx Registrada
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signal sRx0, sRx1 : std_logic; -- Señal Rx Registrada
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begin
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begin
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Countador Principal de Transmision ---
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-- Countador Principal de Transmision ---
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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txCntr:
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txCntr:
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process(rst,clk)
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process(rst,clk)
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variable counter : integer range 0 to 1023;
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variable counter : integer range 0 to 1023;
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begin
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begin
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if rst = '0' then
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if rst = '0' then
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bit1 <= '0';
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bit1 <= '0';
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counter := 0;
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counter := 0;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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bit1 <= '0';
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bit1 <= '0';
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if sEnableTxCounter ='0' then
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if sEnableTxCounter ='0' then
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counter := 0;
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counter := 0;
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elsif counter = TBIT then
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elsif counter = TBIT then
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bit1 <= '1';
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bit1 <= '1';
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counter := 0;
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counter := 0;
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else
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else
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counter := counter + 1;
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counter := counter + 1;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Countador Principal de Transmision (115200 bps : 1/2 Baudio con 8 Ticks => 1 Tick / 54 ns)
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-- Countador Principal de Transmision (115200 bps : 1/2 Baudio con 8 Ticks => 1 Tick / 54 ns)
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-- Adicionalmente este contador usa la señal sSyncRxCounter, para resetearlo.
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-- Adicionalmente este contador usa la señal sSyncRxCounter, para resetearlo.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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rxCntr:
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rxCntr:
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process(rst, clk)
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process(rst, clk)
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variable counter : integer range 0 to 1023;
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variable counter : integer range 0 to 1023;
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begin
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begin
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if rst = '0' then
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if rst = '0' then
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bit2 <= '0';
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bit2 <= '0';
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counter := 0;
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counter := 0;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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bit2 <= '0';
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bit2 <= '0';
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if sSyncRxCounter = '1' then
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if sSyncRxCounter = '1' then
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counter:=0;
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counter:=0;
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elsif counter = THALF_BIT then
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elsif counter = THALF_BIT then
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-- Reset el contador y marcar medio bit.
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-- Reset el contador y marcar medio bit.
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bit2 <= '1';
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bit2 <= '1';
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counter := 0;
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counter := 0;
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else
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else
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counter := counter + 1;
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counter := counter + 1;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Maquina de estado de transmision
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-- Maquina de estado de transmision
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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txFSM:
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txFSM:
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process(rst, clk)
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process(rst, clk)
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variable counter : integer range 0 to 15;
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variable counter : integer range 0 to 15;
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begin
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begin
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if rst = '0' then
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if rst = '0' then
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-- Seleccionar estado de espera.
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-- Seleccionar estado de espera.
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sTxState <= WAITING_LOAD_TX;
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sTxState <= WAITING_LOAD_TX;
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-- Registro de corrimiento en 1. De esa manera se pone automaticamente la linea de transmision en 1.
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-- Registro de corrimiento en 1. De esa manera se pone automaticamente la linea de transmision en 1.
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sShiftTxData <= (others => '1');
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sShiftTxData <= (others => '1');
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-- Deshabilitar el contador de transmision (canal libre).
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-- Deshabilitar el contador de transmision (canal libre).
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sEnableTxCounter <= '0';
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sEnableTxCounter <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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case sTxState is
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case sTxState is
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when WAITING_LOAD_TX =>
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when WAITING_LOAD_TX =>
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if TxLoad = '1' then
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if TxLoad = '1' then
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-- Cargar Dato
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-- Cargar Dato
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sTxDataInReg <= TxDataIn;
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sTxDataInReg <= TxDataIn;
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-- Siguiente estado : Cargar bit
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-- Siguiente estado : Cargar bit
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sTxState <= SET_STARTBIT_TX;
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sTxState <= SET_STARTBIT_TX;
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-- Habilitar el contador de Tx (canal ocupado)
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-- Habilitar el contador de Tx (canal ocupado)
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sEnableTxCounter <= '1';
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sEnableTxCounter <= '1';
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end if;
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end if;
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when SET_STARTBIT_TX =>
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when SET_STARTBIT_TX =>
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if bit1 = '1' then -- Esperar a que transcurra el tiempo de un bit.
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if bit1 = '1' then -- Esperar a que transcurra el tiempo de un bit.
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-- 0 avo bit
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-- 0 avo bit
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counter := 1;
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counter := 1;
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-- Colocar el startbit
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-- Colocar el startbit
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sShiftTxData(9 downto 0) <= '1' & sTxDataInReg(7 downto 0) & '0'; -- Enviar START BIT
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sShiftTxData(9 downto 0) <= '1' & sTxDataInReg(7 downto 0) & '0'; -- Enviar START BIT
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-- Pasar a esperar tbit para colocar el siguiente bit de datos en la linea tx
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-- Pasar a esperar tbit para colocar el siguiente bit de datos en la linea tx
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sTxState <= SET_NBIT_TX; -- Cargar siguiente dato
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sTxState <= SET_NBIT_TX; -- Cargar siguiente dato
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end if;
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end if;
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when SET_NBIT_TX =>
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when SET_NBIT_TX =>
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if bit1 = '1' then -- Paso un bit
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if bit1 = '1' then -- Paso un bit
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-- Contar el numero de datos enviados
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-- Contar el numero de datos enviados
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counter := counter + 1; -- Calcular el numero de datos - 1 enviados
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counter := counter + 1; -- Calcular el numero de datos - 1 enviados
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-- Correr el registro de y transmitir el ultimo bit.
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-- Correr el registro de y transmitir el ultimo bit.
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sShiftTxData(9 downto 0) <= '1' & sShiftTxData(9 downto 1);
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sShiftTxData(9 downto 0) <= '1' & sShiftTxData(9 downto 1);
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if counter = 10 then -- 10 bits enviados parar.
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if counter = 10 then -- 10 bits enviados parar.
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-- Ir al estado de finalizacion de la transmision
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-- Ir al estado de finalizacion de la transmision
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sTxState <= FINISH_TX;
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sTxState <= FINISH_TX;
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end if;
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end if;
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end if;
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end if;
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when FINISH_TX => -- stop bit
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when FINISH_TX => -- stop bit
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if bit1 = '1' then
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if bit1 = '1' then
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-- Estado Ocioso
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-- Estado Ocioso
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sTxState <= WAITING_LOAD_TX;
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sTxState <= WAITING_LOAD_TX;
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-- Deshabilitar el contador de transmision y declarar el canal de transmision libre.
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-- Deshabilitar el contador de transmision y declarar el canal de transmision libre.
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sEnableTxCounter <= '0';
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sEnableTxCounter <= '0';
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end if;
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end if;
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when others =>
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when others =>
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-- Si no se sabe el estado entonces ir a finish para liberar el canal.
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-- Si no se sabe el estado entonces ir a finish para liberar el canal.
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sTxState <= FINISH_TX;
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sTxState <= FINISH_TX;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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-- Declarar el canal como ocupado o desocupado si el contador de transmision está encendido o apagado respectivamente
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-- Declarar el canal como ocupado o desocupado si el contador de transmision está encendido o apagado respectivamente
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TxBusy <= sEnableTxCounter;
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TxBusy <= sEnableTxCounter;
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Tx <= sShiftTxData(0);
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Tx <= sShiftTxData(0);
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Reception process
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-- Reception process
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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rxFSM: process(rst, clk)
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rxFSM: process(rst, clk)
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variable counter : integer range 0 to 127;
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variable counter : integer range 0 to 127;
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begin
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begin
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if rst = '0' then
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if rst = '0' then
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RxDataOut <= (others => '1');
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RxDataOut <= (others => '1');
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RxRdy <= '0';
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RxRdy <= '0';
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sShiftRxData <= (others => '1');
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sShiftRxData <= (others => '1');
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sRxState <= WAIT_START_BIT;
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sRxState <= WAIT_START_BIT;
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sRx0<='1';
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sRx0<='1';
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sRx1<='1';
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sRx1<='1';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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RxRdy <= '0';
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RxRdy <= '0';
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sSyncRxCounter <='0';
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sSyncRxCounter <='0';
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-- Doble FF para la sincronizaciòn de Rx. Esto no funciona muy bien con PLL.
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-- Doble FF para la sincronizaciòn de Rx. Esto no funciona muy bien con PLL.
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-- Preguntar a Alejandra.
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-- Preguntar a Alejandra.
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sRx0 <= Rx;
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sRx0 <= Rx;
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sRx1 <= sRx0;
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sRx1 <= sRx0;
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case sRxState is
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case sRxState is
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when WAIT_START_BIT => -- Wait start bit
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when WAIT_START_BIT => -- Wait start bit
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if (sRx1 and not(sRx0))='1' then -- Si hay un Flanco de bajada
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if (sRx1 and not(sRx0))='1' then -- Si hay un Flanco de bajada
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-- Siguiente estado : esperar que pase el bit de start
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-- Siguiente estado : esperar que pase el bit de start
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sRxState <= HOLD_STARTBIT_RX;
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sRxState <= HOLD_STARTBIT_RX;
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-- Sincronizacion contador
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-- Sincronizacion contador
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sSyncRxCounter <='1';
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sSyncRxCounter <='1';
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-- Vamos en el primer bit.
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-- Vamos en el primer bit.
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counter := 0;
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counter := 0;
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end if;
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end if;
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when HOLD_STARTBIT_RX =>
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when HOLD_STARTBIT_RX =>
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if bit2 = '1' then -- Nos encontramos en la mitad del baudio del start bit. Ahora lo muestreamos sin cargarlo ;)
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if bit2 = '1' then -- Nos encontramos en la mitad del baudio del start bit. Ahora lo muestreamos sin cargarlo ;)
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sRxState <= WAIT_FOR_NEW_BIT_RX; -- Siguiente estado es detectar nuevo bit.
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sRxState <= WAIT_FOR_NEW_BIT_RX; -- Siguiente estado es detectar nuevo bit.
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end if;
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end if;
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when WAIT_FOR_NEW_BIT_RX =>
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when WAIT_FOR_NEW_BIT_RX =>
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if bit2 = '1' then -- En este momento nos encontramos en el comienzo de un bit.
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if bit2 = '1' then -- En este momento nos encontramos en el comienzo de un bit.
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if counter = 8 then -- Si hemos leido el OCTAVO bit entonces el que sigue es el NOVENO bit (STOP BIT)
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if counter = 8 then -- Si hemos leido el OCTAVO bit entonces el que sigue es el NOVENO bit (STOP BIT)
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sRxState <= SAMPLE_STOPBIT_RX; -- Ir al estado de lectura del stop bit.
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sRxState <= SAMPLE_STOPBIT_RX; -- Ir al estado de lectura del stop bit.
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else
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else
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sRxState <= SAMPLE_BIT_RX;-- Ir al estado de carga de un bit de datos.
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sRxState <= SAMPLE_BIT_RX;-- Ir al estado de carga de un bit de datos.
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end if;
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end if;
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end if;
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end if;
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when SAMPLE_BIT_RX =>
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when SAMPLE_BIT_RX =>
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if bit2 = '1' then -- Nos encontramos en la mitad de un baudio. Muestrear el bit correspondiente.
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if bit2 = '1' then -- Nos encontramos en la mitad de un baudio. Muestrear el bit correspondiente.
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--Contar el numero de bits leidos.
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--Contar el numero de bits leidos.
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counter := counter + 1;
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counter := counter + 1;
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--Cargar el bit que se encuentra en la linea RX (después del flip flop para evitar metaestabilidad)
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--Cargar el bit que se encuentra en la linea RX (después del flip flop para evitar metaestabilidad)
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sShiftRxData(7 downto 0) <= sRx0 & sShiftRxData(7 downto 1);
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sShiftRxData(7 downto 0) <= sRx0 & sShiftRxData(7 downto 1);
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-- Siguiente estado : Detectar nuevo baudio.
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-- Siguiente estado : Detectar nuevo baudio.
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sRxState <= WAIT_FOR_NEW_BIT_RX;
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sRxState <= WAIT_FOR_NEW_BIT_RX;
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end if;
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end if;
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when SAMPLE_STOPBIT_RX =>
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when SAMPLE_STOPBIT_RX =>
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if bit2 = '1' then -- Estamos en la mitad del stop bit.
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if bit2 = '1' then -- Estamos en la mitad del stop bit.
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-- Cargar el dato del shift register al buffer de salida.
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-- Cargar el dato del shift register al buffer de salida.
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RxDataOut <= sShiftRxData;
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RxDataOut <= sShiftRxData;
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-- Siguiente estado: Ocioso, esperando por un start bit.
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-- Siguiente estado: Ocioso, esperando por un start bit.
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sRxState <= WAIT_START_BIT;
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sRxState <= WAIT_START_BIT;
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-- Avisar que está listo el dato.
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-- Avisar que está listo el dato.
|
RxRdy <='1';
|
RxRdy <='1';
|
|
|
end if;
|
end if;
|
|
|
|
|
when others =>
|
when others =>
|
|
|
sRxState <= WAIT_START_BIT;
|
sRxState <= WAIT_START_BIT;
|
|
|
end case;
|
end case;
|
|
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
|
|
end rtl;
|
end rtl;
|
|
|
|
|
