-- Author : Julian Andres Guarin Reyes.
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-- Author : Julian Andres Guarin Reyes.
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-- Project : JART, Just Another Ray Tracer.
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-- Project : JART, Just Another Ray Tracer.
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-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
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-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
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-- This code was entirely written by Julian Andres Guarin Reyes.
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-- This code was entirely written by Julian Andres Guarin Reyes.
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-- The following code is licensed under GNU Public License
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-- The following code is licensed under GNU Public License
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-- http://www.gnu.org/licenses/gpl-3.0.txt.
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-- http://www.gnu.org/licenses/gpl-3.0.txt.
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-- This file is part of JART (Just Another Ray Tracer).
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-- This file is part of JART (Just Another Ray Tracer).
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-- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
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-- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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-- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
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-- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>.
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-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>.
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-- 16X50M Intersection Tests
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-- 16X50M Intersection Tests
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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package powerGrid is
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package powerGrid is
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--A one stage pipe a+b+c with w width bits in input as well as output.
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--A one stage pipe a+b+c with w width bits in input as well as output.
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component p1ax
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component p1ax
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generic ( W : integer := 36 );
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generic ( W : integer := 36 );
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port ( clk : in std_logic;
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port ( clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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enable : in std_logic;
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enable : in std_logic;
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dataa : in std_logic_vector(W-1 downto 0);
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dataa : in std_logic_vector(W-1 downto 0);
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datab : in std_logic_vector(W-1 downto 0);
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datab : in std_logic_vector(W-1 downto 0);
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datac : in std_logic_vector(W-1 downto 0);
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datac : in std_logic_vector(W-1 downto 0);
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result : out std_logic_vector(W-1 downto 0)
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result : out std_logic_vector(W-1 downto 0)
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);
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);
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end component;
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end component;
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-- A 1 stage pipe 18x18 multiplier. On Cycle III devices is a M-R (Multiplier, Register). (Should be generated using a synthesis tool....).
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-- A 1 stage pipe 18x18 multiplier. On Cycle III devices is a M-R (Multiplier, Register). (Should be generated using a synthesis tool....).
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component p1m18
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component p1m18
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port (
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port (
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aclr : in std_logic ;
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aclr : in std_logic ;
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clken : in std_logic ;
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clken : in std_logic ;
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clock : in std_logic ;
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clock : in std_logic ;
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dataa : in std_logic_vector (17 downto 0);
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dataa : in std_logic_vector (17 downto 0);
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datab : in std_logic_vector (17 downto 0);
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datab : in std_logic_vector (17 downto 0);
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result : out std_logic_vector (35 downto 0)
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result : out std_logic_vector (35 downto 0)
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);
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);
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end component;
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end component;
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-- Signed "less than"
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-- Signed "less than"
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component sl32
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component sl32
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port (
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port (
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dataa : in std_logic_vector (31 downto 0);
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dataa : in std_logic_vector (31 downto 0);
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datab : in std_logic_vector (31 downto 0);
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datab : in std_logic_vector (31 downto 0);
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AlB : out std_logic
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AlB : out std_logic
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);
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);
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end component;
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end component;
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-- Signed "greater than"
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-- Signed "greater than"
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component sge32
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component sge32
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port (
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port (
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dataa : in std_logic_vector (31 downto 0);
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dataa : in std_logic_vector (31 downto 0);
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datab : in std_logic_vector (31 downto 0);
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datab : in std_logic_vector (31 downto 0);
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AgeB : out std_logic
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AgeB : out std_logic
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);
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);
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end component;
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end component;
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-- Minimun distance Comparison
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-- Minimun distance Comparison
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component dComparisonCell
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component dComparisonCell
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generic ( W : integer := 32; -- V.D, minDistance and selectD Width
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generic ( W : integer := 32; -- V.D, minDistance and selectD Width
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idColW : integer := 2; -- Column Sphere ID width. 1 = 2 columns max, 2= 4 colums max... and so on.
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idColW : integer := 2; -- Column Sphere ID width. 1 = 2 columns max, 2= 4 colums max... and so on.
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idCol : integer := 0 -- Column Id
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idCol : integer := 0 -- Column Id
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);
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);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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cIdd : in std_logic_vector (idColW - 1 downto 0); -- This is the reference column identification input.
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cIdd : in std_logic_vector (idColW - 1 downto 0); -- This is the reference column identification input.
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cIdq : out std_logic_vector (idColW - 1 downto 0); -- This is the result column identification output.
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cIdq : out std_logic_vector (idColW - 1 downto 0); -- This is the result column identification output.
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refvd : in std_logic_vector (W - 1 downto 0); -- This is the reference projection incoming from the previous cell.
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refvd : in std_logic_vector (W - 1 downto 0); -- This is the reference projection incoming from the previous cell.
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colvd : in std_logic_vector (W - 1 downto 0); -- This is the sphere position over the ray traced vector projection.
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colvd : in std_logic_vector (W - 1 downto 0); -- This is the sphere position over the ray traced vector projection.
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selvd : out std_logic_vector (W - 1 downto 0) -- This is the smallest value between refvd and colvd.
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selvd : out std_logic_vector (W - 1 downto 0) -- This is the smallest value between refvd and colvd.
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);
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);
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end component;
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end component;
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-- Dot Product Calculation Cell.
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-- Dot Product Calculation Cell.
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-- A 4 side cell along with an upper side.
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-- A 4 side cell along with an upper side.
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-- V input flows through V output using a data flipflop, so turning V output in the next cell on the next row V Input. V input also flows upwards into the dotproduct 3 stage pipeline.
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-- V input flows through V output using a data flipflop, so turning V output in the next cell on the next row V Input. V input also flows upwards into the dotproduct 3 stage pipeline.
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-- D input flows through D output using a data flipflop, so turning D output in the next column cell. D input also flows upwards into the dotproduct 3 stage.
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-- D input flows through D output using a data flipflop, so turning D output in the next column cell. D input also flows upwards into the dotproduct 3 stage.
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component dotCell
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component dotCell
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generic ( levelW : integer := 18; -- Actual Level Width
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generic ( levelW : integer := 18; -- Actual Level Width
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nLevelW : integer := 32); -- Next Level Width
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nLevelW : integer := 32); -- Next Level Width
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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-- Object control.
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-- Object control.
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nxtSphere : in std_logic; -- This bit controls when the sphere center goes to the next row.
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nxtSphere : in std_logic; -- This bit controls when the sphere center goes to the next row.
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nxtRay : in std_logic; -- This bit controls when the ray goes to the next column.
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nxtRay : in std_logic; -- This bit controls when the ray goes to the next column.
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-- First Side.
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-- First Side.
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vxInput : in std_logic_vector(levelW-1 downto 0);
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vxInput : in std_logic_vector(levelW-1 downto 0);
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vyInput : in std_logic_vector(levelW-1 downto 0);
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vyInput : in std_logic_vector(levelW-1 downto 0);
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vzInput : in std_logic_vector(levelW-1 downto 0);
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vzInput : in std_logic_vector(levelW-1 downto 0);
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-- Second Side (Opposite to the first one)
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-- Second Side (Opposite to the first one)
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vxOutput : out std_logic_vector(levelW-1 downto 0);
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vxOutput : out std_logic_vector(levelW-1 downto 0);
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vyOutput : out std_logic_vector(levelW-1 downto 0);
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vyOutput : out std_logic_vector(levelW-1 downto 0);
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vzOutput : out std_logic_vector(levelW-1 downto 0);
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vzOutput : out std_logic_vector(levelW-1 downto 0);
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-- Third Side (Perpendicular to the first and second ones)
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-- Third Side (Perpendicular to the first and second ones)
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dxInput : in std_logic_vector(levelW-1 downto 0);
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dxInput : in std_logic_vector(levelW-1 downto 0);
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dyInput : in std_logic_vector(levelW-1 downto 0);
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dyInput : in std_logic_vector(levelW-1 downto 0);
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dzInput : in std_logic_vector(levelW-1 downto 0);
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dzInput : in std_logic_vector(levelW-1 downto 0);
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--Fourth Side (Opposite to the third one)
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--Fourth Side (Opposite to the third one)
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dxOutput : in std_logic_vector(levelW-1 downto 0);
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dxOutput : in std_logic_vector(levelW-1 downto 0);
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dyOutput : in std_logic_vector(levelW-1 downto 0);
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dyOutput : in std_logic_vector(levelW-1 downto 0);
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dzOutput : in std_logic_vector(levelW-1 downto 0);
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dzOutput : in std_logic_vector(levelW-1 downto 0);
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--Fifth Side (Going to the floor right upstairs!)
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--Fifth Side (Going to the floor right upstairs!)
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vdOutput : out std_logic_vector(nLevelW-1 downto 0) -- Dot product.
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vdOutput : out std_logic_vector(nLevelW-1 downto 0) -- Dot product.
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);
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);
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end component;
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end component;
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-- K discriminant comparison.
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-- K discriminant comparison.
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component kComparisonCell
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component kComparisonCell
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generic ( W : integer := 32;
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generic ( W : integer := 32;
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);
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);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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nxtRow : in std_logic; -- Controls when the sphere goes to the next Row.
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nxtSphere : in std_logic; -- Controls when the sphere goes to the next Row.
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pipeOn : in std_logic; -- Enables / Disables the upwarding flow.
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vdinput : in std_logic_vector (W-1 downto 0);
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vdinput : in std_logic_vector (W-1 downto 0);
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kinput : in std_logic_vector (W-1 downto 0);
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kinput : in std_logic_vector (W-1 downto 0);
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koutput : out std_logic_vector (W-1 downto 0);
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koutput : out std_logic_vector (W-1 downto 0);
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vdoutput: out std_logic_vector (W-1 downto 0) -- Selected dot product.
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vdoutput: out std_logic_vector (W-1 downto 0) -- Selected dot product.
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);
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);
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end component;
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end component;
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