// ============================================================================
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// ============================================================================
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// (C) 2011 Robert Finch
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// (C) 2011 Robert Finch
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// All Rights Reserved.
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// All Rights Reserved.
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// robfinch<remove>@opencores.org
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// robfinch<remove>@opencores.org
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//
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//
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// KLC32 - 32 bit CPU
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// KLC32 - 32 bit CPU
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// MEMORY.v - memory operate instructions
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// MEMORY.v - memory operate instructions
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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MEMORY1:
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MEMORY1:
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begin
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begin
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case(mopcode)
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case(mopcode)
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`LW: begin
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`LW: begin
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fc_o <= {sf,2'b01};
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fc_o <= {sf,2'b01};
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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sel_o <= 4'b1111;
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sel_o <= 4'b1111;
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adr_o <= ea;
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adr_o <= ea;
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state <= MEMORY1_ACK;
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state <= MEMORY1_ACK;
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end
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end
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`LH,`LHU:
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`LH,`LHU:
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begin
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begin
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fc_o <= {sf,2'b01};
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fc_o <= {sf,2'b01};
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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sel_o <= ea[1] ? 4'b1100 : 4'b0011;
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sel_o <= ea[1] ? 4'b1100 : 4'b0011;
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adr_o <= ea;
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adr_o <= ea;
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state <= MEMORY1_ACK;
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state <= MEMORY1_ACK;
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end
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end
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`LB,`LBU:
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`LB,`LBU:
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begin
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begin
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fc_o <= {sf,2'b01};
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fc_o <= {sf,2'b01};
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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case(ea[1:0])
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case(ea[1:0])
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2'd0: sel_o <= 4'b0001;
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2'd0: sel_o <= 4'b0001;
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2'd1: sel_o <= 4'b0010;
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2'd1: sel_o <= 4'b0010;
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2'd2: sel_o <= 4'b0100;
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2'd2: sel_o <= 4'b0100;
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2'd3: sel_o <= 4'b1000;
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2'd3: sel_o <= 4'b1000;
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endcase
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endcase
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adr_o <= ea;
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adr_o <= ea;
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state <= MEMORY1_ACK;
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state <= MEMORY1_ACK;
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end
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end
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`SW: begin
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`SW: begin
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fc_o <= {sf,2'b01};
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fc_o <= {sf,2'b01};
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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we_o <= 1'b1;
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we_o <= 1'b1;
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sel_o <= 4'b1111;
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sel_o <= 4'b1111;
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adr_o <= ea;
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adr_o <= ea;
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dat_o <= b;
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dat_o <= b;
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state <= MEMORY1_ACK;
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state <= MEMORY1_ACK;
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end
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end
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`SH: begin
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`SH: begin
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fc_o <= {sf,2'b01};
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fc_o <= {sf,2'b01};
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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we_o <= 1'b1;
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we_o <= 1'b1;
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sel_o <= ea[1] ? 4'b1100 : 4'b0011;
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sel_o <= ea[1] ? 4'b1100 : 4'b0011;
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adr_o <= ea;
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adr_o <= ea;
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dat_o <= {2{b[15:0]}};
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dat_o <= {2{b[15:0]}};
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state <= MEMORY1_ACK;
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state <= MEMORY1_ACK;
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end
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end
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`SB: begin
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`SB: begin
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fc_o <= {sf,2'b01};
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fc_o <= {sf,2'b01};
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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we_o <= 1'b1;
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we_o <= 1'b1;
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case(ea[1:0])
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case(ea[1:0])
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2'd0: sel_o <= 4'b0001;
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2'd0: sel_o <= 4'b0001;
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2'd1: sel_o <= 4'b0010;
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2'd1: sel_o <= 4'b0010;
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2'd2: sel_o <= 4'b0100;
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2'd2: sel_o <= 4'b0100;
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2'd3: sel_o <= 4'b1000;
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2'd3: sel_o <= 4'b1000;
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endcase
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endcase
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adr_o <= ea;
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adr_o <= ea;
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dat_o <= {4{b[7:0]}};
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dat_o <= {4{b[7:0]}};
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state <= MEMORY1_ACK;
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state <= MEMORY1_ACK;
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end
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end
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endcase
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endcase
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end
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end
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MEMORY1_ACK:
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MEMORY1_ACK:
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if (ack_i) begin
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if (ack_i) begin
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case(mopcode)
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case(mopcode)
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`LW: begin
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`LW: begin
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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sel_o <= 4'b0000;
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sel_o <= 4'b0000;
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res <= dat_i;
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res <= dat_i;
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state <= WRITEBACK;
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state <= WRITEBACK;
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end
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end
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`LH: begin
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`LH: begin
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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sel_o <= 4'b0000;
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sel_o <= 4'b0000;
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if (sel_o==4'b0011)
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if (sel_o==4'b0011)
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res <= {{16{dat_i[15]}},dat_i[15:0]};
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res <= {{16{dat_i[15]}},dat_i[15:0]};
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else
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else
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res <= {{16{dat_i[31]}},dat_i[31:16]};
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res <= {{16{dat_i[31]}},dat_i[31:16]};
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state <= WRITEBACK;
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state <= WRITEBACK;
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end
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end
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`LHU: begin
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`LHU: begin
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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sel_o <= 4'b0000;
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sel_o <= 4'b0000;
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if (sel_o==4'b0011)
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if (sel_o==4'b0011)
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res <= {16'd0,dat_i[15:0]};
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res <= {16'd0,dat_i[15:0]};
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else
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else
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res <= {16'd0,dat_i[31:16]};
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res <= {16'd0,dat_i[31:16]};
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state <= WRITEBACK;
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state <= WRITEBACK;
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end
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end
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`LB: begin
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`LB: begin
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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sel_o <= 4'b0000;
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sel_o <= 4'b0000;
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case(sel_o)
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case(sel_o)
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4'b0001: res <= {{24{dat_i[7]}},dat_i[7:0]};
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4'b0001: res <= {{24{dat_i[7]}},dat_i[7:0]};
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4'b0010: res <= {{24{dat_i[15]}},dat_i[15:8]};
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4'b0010: res <= {{24{dat_i[15]}},dat_i[15:8]};
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4'b0100: res <= {{24{dat_i[23]}},dat_i[23:16]};
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4'b0100: res <= {{24{dat_i[23]}},dat_i[23:16]};
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4'b1000: res <= {{24{dat_i[31]}},dat_i[31:24]};
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4'b1000: res <= {{24{dat_i[31]}},dat_i[31:24]};
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endcase
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endcase
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state <= WRITEBACK;
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state <= WRITEBACK;
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end
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end
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`LBU: begin
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`LBU: begin
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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sel_o <= 4'b0000;
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sel_o <= 4'b0000;
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case(sel_o)
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case(sel_o)
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4'b0001: res <= {24'd0,dat_i[7:0]};
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4'b0001: res <= {24'd0,dat_i[7:0]};
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4'b0010: res <= {24'd0,dat_i[15:8]};
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4'b0010: res <= {24'd0,dat_i[15:8]};
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4'b0100: res <= {24'd0,dat_i[23:16]};
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4'b0100: res <= {24'd0,dat_i[23:16]};
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4'b1000: res <= {24'd0,dat_i[31:24]};
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4'b1000: res <= {24'd0,dat_i[31:24]};
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endcase
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endcase
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state <= WRITEBACK;
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state <= WRITEBACK;
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end
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end
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`SW,`SH,`SB:
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`SW,`SH,`SB:
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begin
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begin
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'b0000;
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sel_o <= 4'b0000;
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state <= IFETCH;
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state <= IFETCH;
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end
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end
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endcase
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endcase
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end
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end
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else if (err_i) begin
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else if (err_i) begin
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'b0000;
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sel_o <= 4'b0000;
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vector <= `BUS_ERR_VECTOR;
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vector <= `BUS_ERR_VECTOR;
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state <= TRAP;
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state <= TRAP;
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end
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end
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TAS:
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TAS:
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if (!cyc_o) begin
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if (!cyc_o) begin
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fc_o <= {sf,2'b01};
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fc_o <= {sf,2'b01};
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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sel_o <= 4'b1111;
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sel_o <= 4'b1111;
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adr_o <= ea;
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adr_o <= ea;
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end
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end
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else if (ack_i) begin
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else if (ack_i) begin
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cyc_o <= ~dat_i[31];
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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sel_o <= 4'b0000;
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sel_o <= 4'b0000;
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res <= dat_i;
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res <= dat_i;
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state <= TAS2;
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state <= TAS2;
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end
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end
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else if (err_i) begin
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else if (err_i) begin
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'b0000;
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sel_o <= 4'b0000;
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vector <= `BUS_ERR_VECTOR;
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vector <= `BUS_ERR_VECTOR;
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state <= TRAP;
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state <= TRAP;
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end
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end
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TAS2:
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TAS2:
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if (!res[31]) begin
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if (!res[31]) begin
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if (!stb_o) begin
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if (!stb_o) begin
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fc_o <= {sf,2'b01};
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fc_o <= {sf,2'b01};
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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we_o <= 1'b1;
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we_o <= 1'b1;
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sel_o <= 4'b1111;
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sel_o <= 4'b1111;
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adr_o <= ea;
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adr_o <= ea;
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dat_o <= {1'b1,res[30:0]};
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dat_o <= {1'b1,res[30:0]};
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end
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end
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else if (ack_i) begin
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else if (ack_i) begin
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'b0000;
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sel_o <= 4'b0000;
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state <= WRITEBACK;
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state <= WRITEBACK;
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end
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end
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else if (err_i) begin
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else if (err_i) begin
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'b0000;
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sel_o <= 4'b0000;
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vector <= `BUS_ERR_VECTOR;
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vector <= `BUS_ERR_VECTOR;
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state <= TRAP;
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state <= TRAP;
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end
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end
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end
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end
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else begin
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else begin
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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state <= WRITEBACK;
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state <= WRITEBACK;
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end
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end
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