// ============================================================================
|
// ============================================================================
|
// (C) 2011 Robert Finch
|
// (C) 2011 Robert Finch
|
// All Rights Reserved.
|
// All Rights Reserved.
|
// robfinch<remove>@opencores.org
|
// robfinch<remove>@opencores.org
|
//
|
//
|
// KLC32 - 32 bit CPU
|
// KLC32 - 32 bit CPU
|
// RTS.v - return from subroutine
|
// RTS.v - return from subroutine
|
//
|
//
|
// This source file is free software: you can redistribute it and/or modify
|
// This source file is free software: you can redistribute it and/or modify
|
// it under the terms of the GNU Lesser General Public License as published
|
// it under the terms of the GNU Lesser General Public License as published
|
// by the Free Software Foundation, either version 3 of the License, or
|
// by the Free Software Foundation, either version 3 of the License, or
|
// (at your option) any later version.
|
// (at your option) any later version.
|
//
|
//
|
// This source file is distributed in the hope that it will be useful,
|
// This source file is distributed in the hope that it will be useful,
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
// GNU General Public License for more details.
|
// GNU General Public License for more details.
|
//
|
//
|
// You should have received a copy of the GNU General Public License
|
// You should have received a copy of the GNU General Public License
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
//
|
//
|
// ============================================================================
|
// ============================================================================
|
//
|
//
|
RTS:
|
RTS:
|
if (!cyc_o) begin
|
if (!cyc_o) begin
|
fc_o <= {sf,2'b01};
|
fc_o <= {sf,2'b01};
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= 4'b1111;
|
sel_o <= 4'b1111;
|
adr_o <= sf ? ssp : usp;
|
adr_o <= sf ? ssp : usp;
|
end
|
end
|
else if (ack_i) begin
|
else if (ack_i) begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 4'b0000;
|
sel_o <= 4'b0000;
|
if (sf)
|
if (sf)
|
ssp <= ssp + 32'd4 + ir[21:6];
|
ssp <= ssp + 32'd4 + ir[21:6];
|
else
|
else
|
usp <= usp + 32'd4 + ir[21:6];
|
usp <= usp + 32'd4 + ir[21:6];
|
pc <= {dat_i[31:2],2'b00}+{ir[25:22],2'b00};
|
pc <= {dat_i[31:2],2'b00}+{ir[25:22],2'b00};
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
else if (err_i) begin
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
sel_o <= 4'b0000;
|
|
vector <= `BUS_ERR_VECTOR;
|
|
state <= TRAP;
|
|
end
|
|
|
|
|
|
