`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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/*
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/*
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Top module that will instantiate and connect our DUT (lcd_controller) the ICON, VIO , ILA cores
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Top module that will instantiate and connect our DUT (lcd_controller) the ICON, VIO , ILA cores
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For more information refer to this tutorial (Search in docs if link is broken)
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For more information refer to this tutorial (Search in docs if link is broken)
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http://www.stanford.edu/~phartke/chipscope_tutorial.pdf
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http://www.stanford.edu/~phartke/chipscope_tutorial.pdf
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http://www.stanford.edu/class/ee183/handouts.shtml
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http://www.stanford.edu/class/ee183/handouts.shtml
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*/
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*/
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module top_hw_testbench(
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module top_hw_testbench(
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input clk,
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input clk,
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output hw_lcd_e,
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output hw_lcd_e,
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output hw_lcd_rs,
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output hw_lcd_rs,
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output hw_lcd_rw,
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output hw_lcd_rw,
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output [3:0] hw_lcd_nibble,
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output [3:0] hw_lcd_nibble,
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output hw_strata_flash_disable
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output hw_strata_flash_disable
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);
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);
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// Declare some wires to connect the components
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// Declare some wires to connect the components
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wire rst;
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wire rst;
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wire rs_in,strobe_in;
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wire rs_in,strobe_in;
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wire[7:0] data_in, period_clk_ns;
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wire[7:0] data_in, period_clk_ns;
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wire [3:0] lcd_nibble;
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wire [3:0] lcd_nibble;
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wire lcd_e,lcd_rs,lcd_rw,disable_flash,done;
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wire lcd_e,lcd_rs,lcd_rw,disable_flash,done;
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// Declare the ICON wires
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// Declare the ICON wires
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wire [35: 0] control0;
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wire [35: 0] control0;
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wire [35: 0] control1;
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wire [35: 0] control1;
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// Declare VIO wires
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// Declare VIO wires
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wire [18: 0] async_out;
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wire [18: 0] async_out;
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// Declare ILA wires
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// Declare ILA wires
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wire trig_0;
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wire trig_0;
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wire [16:0] data;
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wire [16:0] data;
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// Declare clock DCM multiplier (3)
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// Declare clock DCM multiplier (3)
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wire clock3x, clock1x, clockbuf;
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wire clock3x, clock1x, clockbuf;
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// Instantiate our Device under test
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// Instantiate our Device under test
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lcd_controller DUT (
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lcd_controller DUT (
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rst,
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rst,
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clock1x,
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clock1x,
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rs_in,
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rs_in,
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data_in,
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data_in,
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strobe_in,
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strobe_in,
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period_clk_ns,
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period_clk_ns,
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lcd_e,
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lcd_e,
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lcd_nibble,
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lcd_nibble,
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lcd_rs,
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lcd_rs,
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lcd_rw,
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lcd_rw,
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disable_flash,
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disable_flash,
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done
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done
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);
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);
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// Instantiate the module of clock multiplier
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// Instantiate the module of clock multiplier
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corePLL instance_name (
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corePLL instance_name (
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.CLKIN_IN(clk),
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.CLKIN_IN(clk),
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.CLKFX_OUT(clock3x),
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.CLKFX_OUT(clock3x),
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.CLKIN_IBUFG_OUT(clockbuf),
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.CLKIN_IBUFG_OUT(clockbuf),
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.CLK0_OUT(clock1x)
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.CLK0_OUT(clock1x)
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);
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);
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coreICON integratedController (
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coreICON integratedController (
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.CONTROL0(control0), // INOUT BUS [35:0]
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.CONTROL0(control0), // INOUT BUS [35:0]
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.CONTROL1(control1)
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.CONTROL1(control1)
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); // INOUT BUS [35:0]
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); // INOUT BUS [35:0]
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coreILA integratedLogicAnalyser (
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coreILA integratedLogicAnalyser (
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.CONTROL(control0), // INOUT BUS [35:0]
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.CONTROL(control0), // INOUT BUS [35:0]
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.CLK(clock3x), // IN
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.CLK(clock3x), // IN
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.DATA(data), // DATA [16:0];
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.DATA(data), // DATA [16:0];
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.TRIG0(trig_0)
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.TRIG0(trig_0)
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); // IN BUS [0:0]
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); // IN BUS [0:0]
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coreVIO VIO_inst
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coreVIO VIO_inst
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(
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(
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.CONTROL(control1), // INOUT BUS [35:0]
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.CONTROL(control1), // INOUT BUS [35:0]
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.CLK(clock3x),
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.CLK(clock1x),// clock1x clock3x
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.SYNC_OUT(async_out)
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.SYNC_OUT(async_out) // The clock must be inverted on the core to garantee a good sample point.
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//.ASYNC_OUT(async_out)
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//.ASYNC_OUT(async_out)
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); // IN BUS [18:0]
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); // IN BUS [18:0]
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assign trig_0 = lcd_e;
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assign trig_0 = lcd_e;
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assign {rst, rs_in, data_in, strobe_in, period_clk_ns} = async_out;
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assign {rst, rs_in, data_in, strobe_in, period_clk_ns} = async_out;
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assign data = {7'd1,lcd_e, lcd_nibble[3:0], lcd_rs, lcd_rw, disable_flash, done, strobe_in};
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assign data = {7'd1,lcd_e, lcd_nibble[3:0], lcd_rs, lcd_rw, disable_flash, done, strobe_in};
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// Send all interest output to outside
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// Send all interest output to outside
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assign hw_lcd_e = lcd_e;
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assign hw_lcd_e = lcd_e;
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assign hw_lcd_rs = lcd_rs;
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assign hw_lcd_rs = lcd_rs;
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assign hw_lcd_rw = lcd_rw;
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assign hw_lcd_rw = lcd_rw;
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assign hw_lcd_nibble = lcd_nibble;
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assign hw_lcd_nibble = lcd_nibble;
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assign hw_strata_flash_disable = disable_flash;
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assign hw_strata_flash_disable = disable_flash;
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endmodule
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endmodule
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