--
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--
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-- Copyright 2011 Martin Schoeberl <masca@imm.dtu.dk>,
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-- Copyright 2011 Martin Schoeberl <masca@imm.dtu.dk>,
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-- Technical University of Denmark, DTU Informatics.
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-- Technical University of Denmark, DTU Informatics.
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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--
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--
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-- 1. Redistributions of source code must retain the above copyright notice,
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-- 1. Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- this list of conditions and the following disclaimer.
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--
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--
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- documentation and/or other materials provided with the distribution.
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER ``AS IS'' AND ANY EXPRESS
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER ``AS IS'' AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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-- NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
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-- NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- The views and conclusions contained in the software and documentation are
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-- The views and conclusions contained in the software and documentation are
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-- those of the authors and should not be interpreted as representing official
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-- those of the authors and should not be interpreted as representing official
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-- policies, either expressed or implied, of the copyright holder.
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-- policies, either expressed or implied, of the copyright holder.
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--
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--
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--
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--
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-- leros_de2-70.vhd
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-- leros_de2-70.vhd
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--
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--
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-- top level for Altera DE2-70 board
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-- top level for Altera DE2-70 board
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--
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--
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-- 2011-02-20 creation
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-- 2011-02-20 creation
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--
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--
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.leros_types.all;
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use work.leros_types.all;
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entity leros_top_de2 is
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entity leros_top_de2 is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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oLEDG : out std_logic_vector(7 downto 0);
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oLEDG : out std_logic_vector(7 downto 0);
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iKEY : in std_logic_vector(3 downto 0);
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iKEY : in std_logic_vector(3 downto 0);
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ser_txd : out std_logic;
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ser_txd : out std_logic;
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ser_rxd : in std_logic
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ser_rxd : in std_logic
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);
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);
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end leros_top_de2;
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end leros_top_de2;
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architecture rtl of leros_top_de2 is
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architecture rtl of leros_top_de2 is
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signal clk_int : std_logic;
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signal clk_int : std_logic;
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-- for generation of internal reset
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-- for generation of internal reset
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signal int_res : std_logic;
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signal int_res : std_logic;
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signal res_cnt : unsigned(2 downto 0) := "000"; -- for the simulation
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signal res_cnt : unsigned(2 downto 0) := "000"; -- for the simulation
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attribute altera_attribute : string;
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attribute altera_attribute : string;
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attribute altera_attribute of res_cnt : signal is "POWER_UP_LEVEL=LOW";
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attribute altera_attribute of res_cnt : signal is "POWER_UP_LEVEL=LOW";
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signal ioout : io_out_type;
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signal ioout : io_out_type;
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signal ioin : io_in_type;
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signal ioin : io_in_type;
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signal outp : std_logic_vector(15 downto 0);
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signal outp : std_logic_vector(15 downto 0);
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signal btn_reg : std_logic_vector(3 downto 0);
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signal btn_reg : std_logic_vector(3 downto 0);
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begin
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begin
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-- clk input is 50 MHz
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-- clk input is 50 MHz
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-- for now 100 MHz is enough
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-- for now 100 MHz is enough
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pll_inst : entity work.pll generic map(
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pll_inst : entity work.pll generic map(
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multiply_by => 2,
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multiply_by => 2,
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divide_by => 1
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divide_by => 1
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)
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)
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port map (
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port map (
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inclk0 => clk,
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inclk0 => clk,
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c0 => clk_int
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c0 => clk_int
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);
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);
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--
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--
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-- internal reset generation
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-- internal reset generation
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-- should include the PLL lock signal
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-- should include the PLL lock signal
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--
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--
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process(clk_int)
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process(clk_int)
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begin
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begin
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if rising_edge(clk_int) then
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if rising_edge(clk_int) then
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if (res_cnt/="111") then
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if (res_cnt/="111") then
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res_cnt <= res_cnt+1;
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res_cnt <= res_cnt+1;
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end if;
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end if;
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int_res <= not res_cnt(0) or not res_cnt(1) or not res_cnt(2);
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int_res <= not res_cnt(0) or not res_cnt(1) or not res_cnt(2);
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end if;
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end if;
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end process;
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end process;
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cpu: entity work.leros
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cpu: entity work.leros
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port map(clk_int, int_res, ioout, ioin);
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port map(clk_int, int_res, ioout, ioin);
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-- ioin.rddata(15 downto 4) <= (others => '0');
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-- ioin.rddata(15 downto 4) <= (others => '0');
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ua: entity work.uart generic map (
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ua: entity work.uart generic map (
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clk_freq => 100000000,
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clk_freq => 100000000,
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baud_rate => 115200,
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baud_rate => 115200,
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txf_depth => 1,
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txf_depth => 1,
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rxf_depth => 1
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rxf_depth => 1
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)
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)
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port map(
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port map(
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clk => clk_int,
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clk => clk_int,
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reset => int_res,
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reset => int_res,
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address => ioout.addr(0),
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address => ioout.addr(0),
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wr_data => ioout.wrdata,
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wr_data => ioout.wrdata,
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rd => ioout.rd,
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rd => ioout.rd,
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wr => ioout.wr,
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wr => ioout.wr,
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rd_data => ioin.rddata,
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rd_data => ioin.rddata,
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txd => ser_txd,
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txd => ser_txd,
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rxd => ser_rxd
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rxd => ser_rxd
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);
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);
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process(clk_int)
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process(clk_int)
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begin
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begin
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if rising_edge(clk_int) then
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if rising_edge(clk_int) then
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if ioout.wr='1' then
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if ioout.wr='1' then
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outp <= ioout.wrdata;
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outp <= ioout.wrdata;
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end if;
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end if;
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oLEDG <= outp(7 downto 0);
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oLEDG <= outp(7 downto 0);
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btn_reg <= iKEY;
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btn_reg <= iKEY;
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-- ioin.rddata(3 downto 0) <= not btn_reg;
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-- ioin.rddata(3 downto 0) <= not btn_reg;
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end if;
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end if;
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end process;
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end process;
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end rtl;
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end rtl;
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