----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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---- Create Date: 13:06:08 07/28/2010 ----
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---- Create Date: 13:06:08 07/28/2010 ----
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---- Design Name: lfsr ----
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---- Design Name: lfsr ----
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---- Project Name: lfsr_randgen ----
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---- Project Name: lfsr_randgen ----
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---- Description: ----
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---- Description: ----
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---- A random number generator based on linear feedback shift ----
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---- A random number generator based on linear feedback shift ----
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---- register(LFSR).A LFSR is a shift register whose input bit is a ----
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---- register(LFSR).A LFSR is a shift register whose input bit is a ----
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---- linear function of its previous state.The detailed documentation ----
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---- linear function of its previous state.The detailed documentation ----
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---- is available in the file named manual.pdf. ----
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---- is available in the file named manual.pdf. ----
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---- ----
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---- ----
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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---- ----
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---- ----
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---- This file is a part of the lfsr_randgen project at ----
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---- This file is a part of the lfsr_randgen project at ----
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---- http://www.opencores.org/ ----
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---- http://www.opencores.org/ ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Author(s): ----
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---- Vipin Lal, lalnitt@gmail.com ----
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---- Vipin Lal, lalnitt@gmail.com ----
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---- ----
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---- ----
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library work;
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library work;
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use work.lfsr_pkg.ALL;
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use work.lfsr_pkg.ALL;
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entity lfsr is
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entity lfsr is
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generic (width : integer := 32);
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generic (width : integer := 4);
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port (clk : in std_logic;
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port (clk : in std_logic;
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set_seed : in std_logic;
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set_seed : in std_logic;
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out_enable : in std_logic;
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seed : in std_logic_vector(width-1 downto 0);
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seed : in std_logic_vector(width-1 downto 0);
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rand_out : out std_logic_vector(width-1 downto 0)
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rand_out : out std_logic_vector(width-1 downto 0)
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);
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);
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end lfsr;
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end lfsr;
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architecture Behavioral of lfsr is
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architecture Behavioral of lfsr is
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begin
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begin
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process(clk,set_seed,out_enable,seed)
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process(clk)
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variable rand_temp : std_logic_vector (width-1 downto 0):=(0 => '1',others => '0');
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variable rand_temp : std_logic_vector (width-1 downto 0):=(0 => '1',others => '0');
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variable temp : std_logic := '0';
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variable temp : std_logic := '0';
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begin
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begin
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if(rising_edge(clk)) then
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if(set_seed = '1') then
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if(set_seed = '1') then
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rand_temp := seed;
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rand_temp := seed;
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elsif(rising_edge(clk)) then
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end if;
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temp := xor_gates(rand_temp);
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temp := xor_gates(rand_temp);
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rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
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rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
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rand_temp(0) := temp;
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rand_temp(0) := temp;
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end if;
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if(out_enable ='1') then
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rand_out <= rand_temp;
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else
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rand_out <= (others => '0');
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end if;
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end if;
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rand_out <= rand_temp;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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