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library ieee,modelsim_lib;
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library ieee,modelsim_lib;
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--use ieee.std_logic_1164.all;
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--use ieee.std_logic_1164.all;
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--use ieee.std_logic_arith.all;
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--use ieee.std_logic_arith.all;
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--use ieee.std_logic_unsigned.all;
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--use ieee.std_logic_unsigned.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.light52_pkg.all;
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use work.light52_pkg.all;
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use modelsim_lib.util.all;
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use modelsim_lib.util.all;
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use std.textio.all;
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use std.textio.all;
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use work.txt_util.all;
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use work.txt_util.all;
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package light52_tb_pkg is
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package light52_tb_pkg is
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-- Maximum line size of for console output log. Lines longer than this will be
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-- Maximum line size of for console output log. Lines longer than this will be
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-- truncated.
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-- truncated.
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constant CONSOLE_LOG_LINE_SIZE : integer := 1024*4;
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constant CONSOLE_LOG_LINE_SIZE : integer := 1024*4;
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type t_addr_array is array(0 to 1) of t_address;
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type t_addr_array is array(0 to 1) of t_address;
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constant BRAM_ADDR_LEN : integer := log2(BRAM_SIZE);
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constant BRAM_ADDR_LEN : integer := log2(BRAM_SIZE);
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subtype t_bram_addr is unsigned(BRAM_ADDR_LEN-1 downto 0);
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subtype t_bram_addr is unsigned(BRAM_ADDR_LEN-1 downto 0);
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type t_opcode_cycle_count is record
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type t_opcode_cycle_count is record
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min : natural; -- Minimum observed cycle count
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min : natural; -- Minimum observed cycle count
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max : natural; -- Maximum observed cycle count
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max : natural; -- Maximum observed cycle count
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exe : natural; -- No. times the opcode was executed
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exe : natural; -- No. times the opcode was executed
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end record t_opcode_cycle_count;
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end record t_opcode_cycle_count;
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type t_cycle_count is array(0 to 255) of t_opcode_cycle_count;
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type t_cycle_count is array(0 to 255) of t_opcode_cycle_count;
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type t_log_info is record
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type t_log_info is record
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acc_input : t_byte;
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acc_input : t_byte;
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load_acc : std_logic;
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load_acc : std_logic;
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a_reg_prev : t_byte;
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a_reg_prev : t_byte;
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update_sp : std_logic;
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update_sp : std_logic;
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sp_reg_prev : t_byte;
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sp_reg_prev : t_byte;
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sp : t_byte;
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sp : t_byte;
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rom_size : natural;
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rom_size : natural;
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update_psw_flags : std_logic_vector(1 downto 0);
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update_psw_flags : std_logic_vector(1 downto 0);
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psw : t_byte;
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psw : t_byte;
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psw_prev : t_byte;
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psw_prev : t_byte;
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psw_update_addr : t_address;
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psw_update_addr : t_address;
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inc_dptr : std_logic;
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inc_dptr : std_logic;
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inc_dptr_prev : std_logic;
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inc_dptr_prev : std_logic;
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dptr : t_address;
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dptr : t_address;
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xdata_we : std_logic;
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xdata_we : std_logic;
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xdata_vma : std_logic;
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xdata_vma : std_logic;
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xdata_addr : t_address;
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xdata_addr : t_address;
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xdata_wr : t_byte;
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xdata_wr : t_byte;
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xdata_rd : t_byte;
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xdata_rd : t_byte;
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code_addr : t_address;
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code_addr : t_address;
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pc : t_address;
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pc : t_address;
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pc_prev : t_address;
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pc_prev : t_address;
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next_pc : t_address;
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next_pc : t_address;
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pc_z : t_addr_array;
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pc_z : t_addr_array;
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ps : t_cpu_state;
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ps : t_cpu_state;
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jump_condition : std_logic;
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rel_jump_target : t_address;
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bram_we : std_logic;
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bram_we : std_logic;
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bram_wr_addr : t_bram_addr;
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bram_wr_addr : t_bram_addr;
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bram_wr_data_p0 : t_byte;
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bram_wr_data_p0 : t_byte;
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sfr_we : std_logic;
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sfr_we : std_logic;
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sfr_wr : t_byte;
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sfr_wr : t_byte;
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sfr_addr : t_byte;
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sfr_addr : t_byte;
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delayed_acc_log : boolean;
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delayed_acc_value : t_byte;
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-- Observed cycle count for all executed opcodes.
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-- Observed cycle count for all executed opcodes.
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cycles : t_cycle_count;
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cycles : t_cycle_count;
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last_opcode : std_logic_vector(7 downto 0);
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last_opcode : std_logic_vector(7 downto 0);
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opcode : std_logic_vector(7 downto 0);
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opcode : std_logic_vector(7 downto 0);
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code_rd : std_logic_vector(7 downto 0);
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code_rd : std_logic_vector(7 downto 0);
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cycle_count : natural;
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cycle_count : natural;
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-- Console log line buffer --------------------------------------
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-- Console log line buffer --------------------------------------
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con_line_buf : string(1 to CONSOLE_LOG_LINE_SIZE);
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con_line_buf : string(1 to CONSOLE_LOG_LINE_SIZE);
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con_line_ix : integer;
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con_line_ix : integer;
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-- Log trigger --------------------------------------------------
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-- Log trigger --------------------------------------------------
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-- Enable logging after fetching from a given address -----------
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-- Enable logging after fetching from a given address -----------
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log_trigger_address : t_address;
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log_trigger_address : t_address;
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log_triggered : boolean;
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log_triggered : boolean;
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end record t_log_info;
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end record t_log_info;
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function hstr(slv: unsigned) return string;
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function hstr(slv: unsigned) return string;
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procedure log_cpu_status(
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procedure log_cpu_status(
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signal info : inout t_log_info;
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signal info : inout t_log_info;
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file l_file : TEXT;
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file l_file : TEXT;
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file con_file : TEXT);
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file con_file : TEXT);
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procedure log_cpu_activity(
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procedure log_cpu_activity(
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signal clk : in std_logic;
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signal clk : in std_logic;
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signal reset : in std_logic;
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signal reset : in std_logic;
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signal done : in std_logic;
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signal done : in std_logic;
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mcu : string;
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mcu : string;
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signal info : inout t_log_info;
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signal info : inout t_log_info;
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rom_size : natural;
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rom_size : natural;
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iname : string;
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iname : string;
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trigger_addr : in t_address;
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trigger_addr : in t_address;
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file l_file : TEXT;
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file l_file : TEXT;
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file con_file : TEXT);
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file con_file : TEXT);
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-- Flush console output to log console file (in case the end of the
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-- Flush console output to log console file (in case the end of the
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-- simulation caught an unterminated line in the buffer)
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-- simulation caught an unterminated line in the buffer)
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procedure log_flush_console(
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procedure log_flush_console(
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signal info : in t_log_info;
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signal info : in t_log_info;
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file con_file : TEXT);
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file con_file : TEXT);
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-- Log cycle count data to file.
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-- Log cycle count data to file.
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procedure log_cycle_counts(
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procedure log_cycle_counts(
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signal info : in t_log_info);
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signal info : in t_log_info);
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end package;
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end package;
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package body light52_tb_pkg is
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package body light52_tb_pkg is
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function hstr(slv: unsigned) return string is
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function hstr(slv: unsigned) return string is
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begin
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begin
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return hstr(std_logic_vector(slv));
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return hstr(std_logic_vector(slv));
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end function hstr;
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end function hstr;
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procedure log_cpu_status(
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procedure log_cpu_status(
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signal info : inout t_log_info;
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signal info : inout t_log_info;
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file l_file : TEXT;
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file l_file : TEXT;
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file con_file : TEXT) is
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file con_file : TEXT) is
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variable bram_wr_addr : unsigned(7 downto 0);
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variable bram_wr_addr : unsigned(7 downto 0);
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variable opc : natural;
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variable opc : natural;
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variable num_cycles : natural;
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variable num_cycles : natural;
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variable jump_logged : boolean := false;
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begin
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begin
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jump_logged := false;
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-- Update the opcode observed cycle counters.
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-- Update the opcode observed cycle counters.
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-- For every opcode, we count the cycles from its decode_0 state to the
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-- For every opcode, we count the cycles from its decode_0 state to the
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-- next fetch_1 state. To this we have to add 2 (one each for states
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-- next fetch_1 state. To this we have to add 2 (one each for states
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-- decode_0 and fetch_1) and we have the cycle count.
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-- decode_0 and fetch_1) and we have the cycle count.
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-- we store the min and the max because of conditional jumps.
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-- we store the min and the max because of conditional jumps.
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if (info.ps=decode_0) then
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if (info.ps=decode_0) then
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info.opcode <= info.last_opcode;
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info.opcode <= info.last_opcode;
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info.cycle_count <= 0;
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info.cycle_count <= 0;
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else
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else
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if (info.ps=fetch_1) then
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if (info.ps=fetch_1) then
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-- In state fetch_1, get the opcode from the bus
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-- In state fetch_1, get the opcode from the bus
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info.last_opcode <= info.code_rd;
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info.last_opcode <= info.code_rd;
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if info.opcode/="UUUUUUUU" then
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if info.opcode/="UUUUUUUU" then
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opc := to_integer(unsigned(info.opcode));
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opc := to_integer(unsigned(info.opcode));
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num_cycles := info.cycle_count + 2;
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num_cycles := info.cycle_count + 2;
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if info.cycles(opc).min > num_cycles then
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if info.cycles(opc).min > num_cycles then
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info.cycles(opc).min <= num_cycles;
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info.cycles(opc).min <= num_cycles;
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end if;
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end if;
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if info.cycles(opc).max < num_cycles then
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if info.cycles(opc).max < num_cycles then
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info.cycles(opc).max <= num_cycles;
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info.cycles(opc).max <= num_cycles;
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end if;
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end if;
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info.cycles(opc).exe <= info.cycles(opc).exe + 1;
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info.cycles(opc).exe <= info.cycles(opc).exe + 1;
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end if;
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end if;
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end if;
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end if;
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info.cycle_count <= info.cycle_count + 1;
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info.cycle_count <= info.cycle_count + 1;
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end if;
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end if;
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bram_wr_addr := info.bram_wr_addr(7 downto 0);
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bram_wr_addr := info.bram_wr_addr(7 downto 0);
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-- Log writes to IDATA BRAM
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-- Log writes to IDATA BRAM
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if info.bram_we='1' then
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if info.bram_we='1' then
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print(l_file, "("& hstr(info.pc)& ") ["& hstr(bram_wr_addr) & "] = "&
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print(l_file, "("& hstr(info.pc)& ") ["& hstr(bram_wr_addr) & "] = "&
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hstr(info.bram_wr_data_p0) );
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hstr(info.bram_wr_data_p0) );
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end if;
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end if;
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-- Log writes to SFRs
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-- Log writes to SFRs
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if info.sfr_we = '1' then
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if info.sfr_we = '1' then
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print(l_file, "("& hstr(info.pc)& ") SFR["&
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print(l_file, "("& hstr(info.pc)& ") SFR["&
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hstr(info.sfr_addr)& "] = "& hstr(info.sfr_wr));
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hstr(info.sfr_addr)& "] = "& hstr(info.sfr_wr));
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end if;
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end if;
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-- Log jumps
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-- FIXME remove internal state dependency
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--if info.ps = jrb_bit_3 and info.jump_condition='1' then
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-- Catch attempts to jump to addresses out of the ROM bounds -- assume
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-- mirroring is not expected to be useful in this case.
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-- Note it remains possible to just run into uninitialized ROM areas
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-- or out of ROM bounds, we're not checking any of that.
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--assert info.next_pc < info.rom_size
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--report "Jump to unmapped code address "& hstr(info.next_pc)&
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-- "h at "& hstr(info.pc)& "h. Simulation stopped."
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--severity failure;
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-- print(l_file, "("& hstr(info.pc)& ") PC = "&
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-- hstr(info.rel_jump_target) );
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--end if;
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-- Log ACC updates.
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-- Log ACC updates.
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-- Note we exclude the 'intermediate update' of ACC in DA instruction.
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-- Note we exclude the 'intermediate update' of ACC in DA instruction, and
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-- we have to deal with another tricky special case:
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-- the JBC instruction needs the ACC change log delayed so that it appears
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-- after the PC change log -- a nasty hack meant to avoid a nastier hack
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-- in the SW simulator logging code.
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if (info.load_acc='1' and info.ps/=alu_daa_0) then
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if (info.load_acc='1' and info.ps/=alu_daa_0) then
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if info.a_reg_prev /= info.acc_input then
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if info.a_reg_prev /= info.acc_input then
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if info.ps = jrb_bit_2 then -- this state is only used in JBC
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info.delayed_acc_log <= true;
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info.delayed_acc_value <= info.acc_input;
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else
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print(l_file, "("& hstr(info.pc)& ") A = "&
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print(l_file, "("& hstr(info.pc)& ") A = "&
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hstr(info.acc_input) );
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hstr(info.acc_input) );
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end if;
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end if;
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end if;
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info.a_reg_prev <= info.acc_input;
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info.a_reg_prev <= info.acc_input;
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end if;
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end if;
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-- Log XRAM writes
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-- Log XRAM writes
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if (info.xdata_we='1') then
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if (info.xdata_we='1') then
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print(l_file, "("& hstr(info.pc)& ") <"&
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print(l_file, "("& hstr(info.pc)& ") <"&
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hstr(info.xdata_addr)& "> = "&
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hstr(info.xdata_addr)& "> = "&
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hstr(info.xdata_wr) );
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hstr(info.xdata_wr) );
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end if;
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end if;
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-- Log SP explicit and implicit updates.
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-- Log SP explicit and implicit updates.
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-- At the beginning of each instruction we log the SP change if there is
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-- At the beginning of each instruction we log the SP change if there is
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-- any. SP changes at different times for different instructions. This way,
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-- any. SP changes at different times for different instructions. This way,
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-- the log is always done at the end of the instruction execution, as is
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-- the log is always done at the end of the instruction execution, as is
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-- done in B51.
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-- done in B51.
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if (info.ps=fetch_1) then
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if (info.ps=fetch_1) then
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if info.sp_reg_prev /= info.sp then
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if info.sp_reg_prev /= info.sp then
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print(l_file, "("& hstr(info.pc)& ") SP = "&
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print(l_file, "("& hstr(info.pc)& ") SP = "&
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hstr(info.sp) );
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hstr(info.sp) );
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end if;
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end if;
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info.sp_reg_prev <= info.sp;
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info.sp_reg_prev <= info.sp;
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end if;
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end if;
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-- Log DPTR increments
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-- Log DPTR increments
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if (info.inc_dptr_prev='1') then
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if (info.inc_dptr_prev='1') then
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print(l_file, "("& hstr(info.pc)& ") DPTR = "&
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print(l_file, "("& hstr(info.pc)& ") DPTR = "&
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hstr(info.dptr) );
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hstr(info.dptr) );
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end if;
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end if;
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info.inc_dptr_prev <= info.inc_dptr;
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info.inc_dptr_prev <= info.inc_dptr;
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-- Console logging ---------------------------------------------------------
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-- Console logging ---------------------------------------------------------
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-- TX data may come from the high or low byte (opcodes.s
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-- TX data may come from the high or low byte (opcodes.s
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-- uses high byte, no_op.c uses low)
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-- uses high byte, no_op.c uses low)
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if info.sfr_we = '1' and info.sfr_addr = X"99" then
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if info.sfr_we = '1' and info.sfr_addr = X"99" then
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-- UART TX data goes to output after a bit of line-buffering
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-- UART TX data goes to output after a bit of line-buffering
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-- and editing
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-- and editing
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if info.sfr_wr = X"0A" then
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if info.sfr_wr = X"0A" then
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-- CR received: print output string and clear it
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-- CR received: print output string and clear it
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print(con_file, info.con_line_buf(1 to info.con_line_ix));
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print(con_file, info.con_line_buf(1 to info.con_line_ix));
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info.con_line_ix <= 1;
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info.con_line_ix <= 1;
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info.con_line_buf <= (others => ' ');
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info.con_line_buf <= (others => ' ');
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elsif info.sfr_wr = X"0D" then
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elsif info.sfr_wr = X"0D" then
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-- ignore LF
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-- ignore LF
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else
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else
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-- append char to output string
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-- append char to output string
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if info.con_line_ix < info.con_line_buf'high then
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if info.con_line_ix < info.con_line_buf'high then
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info.con_line_buf(info.con_line_ix) <=
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info.con_line_buf(info.con_line_ix) <=
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character'val(to_integer(info.sfr_wr));
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character'val(to_integer(info.sfr_wr));
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info.con_line_ix <= info.con_line_ix + 1;
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info.con_line_ix <= info.con_line_ix + 1;
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--print(str(info.con_line_ix));
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--print(str(info.con_line_ix));
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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-- Log jumps
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-- Log jumps
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-- FIXME remove internal state dependency
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-- FIXME remove internal state dependency
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if info.ps = long_jump or
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if info.ps = long_jump or
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info.ps = lcall_4 or
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info.ps = lcall_4 or
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info.ps = jmp_adptr_0 or
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info.ps = jmp_adptr_0 or
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info.ps = ret_3 or
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info.ps = ret_3 or
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info.ps = rel_jump or
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info.ps = rel_jump or
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info.ps = cjne_a_imm_2 or
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info.ps = cjne_a_imm_2 or
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info.ps = cjne_rn_imm_3 or
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info.ps = cjne_rn_imm_3 or
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info.ps = cjne_ri_imm_5 or
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info.ps = cjne_ri_imm_5 or
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info.ps = cjne_a_dir_3 or
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info.ps = cjne_a_dir_3 or
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info.ps = jrb_bit_4 or
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info.ps = jrb_bit_4 or
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info.ps = djnz_dir_4
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info.ps = djnz_dir_4
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then
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then
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-- Catch attempts to jump to addresses out of the ROM bounds -- assume
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-- Catch attempts to jump to addresses out of the ROM bounds -- assume
|
-- mirroring is not expected to be useful in this case.
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-- mirroring is not expected to be useful in this case.
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-- Note it remains possible to just run into uninitialized ROM areas
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-- Note it remains possible to just run into uninitialized ROM areas
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-- or out of ROM bounds, we're not checking any of that.
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-- or out of ROM bounds, we're not checking any of that.
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assert info.next_pc < info.rom_size
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assert info.next_pc < info.rom_size
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report "Jump to unmapped code address "& hstr(info.next_pc)&
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report "Jump to unmapped code address "& hstr(info.next_pc)&
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"h at "& hstr(info.pc)& "h. Simulation stopped."
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"h at "& hstr(info.pc)& "h. Simulation stopped."
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severity failure;
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severity failure;
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print(l_file, "("& hstr(info.pc)& ") PC = "&
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print(l_file, "("& hstr(info.pc)& ") PC = "&
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hstr(info.next_pc) );
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hstr(info.next_pc) );
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jump_logged := true;
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end if;
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-- If this instruction needs the ACC change log delayed, display it now
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-- but only if the PC change has been already logged.
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-- This only happens in instructions that jump AND can modify ACC: JBC.
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-- The PSW change, if any, is delayed too, see below.
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if info.delayed_acc_log and jump_logged then
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print(l_file, "("& hstr(info.pc)& ") A = "&
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hstr(info.delayed_acc_value) );
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info.delayed_acc_log <= false;
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end if;
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end if;
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-- Log PSW implicit updates: first, whenever the PSW is updated, save the PC
|
-- Log PSW implicit updates: first, whenever the PSW is updated, save the PC
|
-- for later reference...
|
-- for later reference...
|
if (info.update_psw_flags(0)='1' or info.load_acc='1') then
|
if (info.update_psw_flags(0)='1' or info.load_acc='1') then
|
info.psw_update_addr <= info.pc;
|
info.psw_update_addr <= info.pc;
|
end if;
|
end if;
|
-- ...then, when the PSW change is actually detected, log it along with the
|
-- ...then, when the PSW change is actually detected, log it along with the
|
-- PC value we saved before.
|
-- PC value we saved before.
|
-- The PSW changes late in the instruction cycle and we need this trick to
|
-- The PSW changes late in the instruction cycle and we need this trick to
|
-- keep the logs ordered.
|
-- keep the logs ordered.
|
if (info.psw) /= (info.psw_prev) then
|
-- Note that if the ACC log is delayed, the PSW log is delayed too!
|
|
if (info.psw) /= (info.psw_prev) and not info.delayed_acc_log then
|
print(l_file, "("& hstr(info.psw_update_addr)& ") PSW = "& hstr(info.psw) );
|
print(l_file, "("& hstr(info.psw_update_addr)& ") PSW = "& hstr(info.psw) );
|
info.psw_prev <= info.psw;
|
info.psw_prev <= info.psw;
|
end if;
|
end if;
|
|
|
-- Stop the simulation if we find an unconditional, one-instruction endless
|
-- Stop the simulation if we find an unconditional, one-instruction endless
|
-- loop. This will not catch multi-instruction endless loops and is only
|
-- loop. This will not catch multi-instruction endless loops and is only
|
-- intended to replicate the behavior of B51 and give the SW a means to
|
-- intended to replicate the behavior of B51 and give the SW a means to
|
-- cleanly end the simulation.
|
-- cleanly end the simulation.
|
-- FIXME use some jump signal, not a single state
|
-- FIXME use some jump signal, not a single state
|
if info.ps = long_jump and (info.pc = info.next_pc) then
|
if info.ps = long_jump and (info.pc = info.next_pc) then
|
-- Before quitting, optionally log cycle count table to separate file.
|
-- Before quitting, optionally log cycle count table to separate file.
|
log_cycle_counts(info);
|
log_cycle_counts(info);
|
|
|
assert false
|
assert false
|
report "NONE. Endless loop encountered. Simulation terminated."
|
report "NONE. Endless loop encountered. Simulation terminated."
|
severity failure;
|
severity failure;
|
end if;
|
end if;
|
|
|
-- Update the address of the current instruction.
|
-- Update the address of the current instruction.
|
-- The easiest way to know the address of the current instruction is to look
|
-- The easiest way to know the address of the current instruction is to look
|
-- at the state machine; when in state decode_0, we know that the opcode
|
-- at the state machine; when in state decode_0, we know that the opcode
|
-- address was on code_addr bus two cycles earlier.
|
-- address was on code_addr bus two cycles earlier.
|
-- We don't need to track the PC value cycle by cycle, we only need info.pc
|
-- We don't need to track the PC value cycle by cycle, we only need info.pc
|
-- to be valid when the logs above are executed, and that's always after
|
-- to be valid when the logs above are executed, and that's always after
|
-- state decode_0.
|
-- state decode_0.
|
info.pc_z(1) <= info.pc_z(0);
|
info.pc_z(1) <= info.pc_z(0);
|
info.pc_z(0) <= info.code_addr;
|
info.pc_z(0) <= info.code_addr;
|
if info.ps = decode_0 then
|
if info.ps = decode_0 then
|
info.pc_prev <= info.pc;
|
info.pc_prev <= info.pc;
|
info.pc <= info.pc_z(1);
|
info.pc <= info.pc_z(1);
|
end if;
|
end if;
|
|
|
end procedure log_cpu_status;
|
end procedure log_cpu_status;
|
|
|
procedure log_cpu_activity(
|
procedure log_cpu_activity(
|
signal clk : in std_logic;
|
signal clk : in std_logic;
|
signal reset : in std_logic;
|
signal reset : in std_logic;
|
signal done : in std_logic;
|
signal done : in std_logic;
|
mcu : string;
|
mcu : string;
|
signal info : inout t_log_info;
|
signal info : inout t_log_info;
|
rom_size : natural;
|
rom_size : natural;
|
iname : string;
|
iname : string;
|
trigger_addr : in t_address;
|
trigger_addr : in t_address;
|
file l_file : TEXT;
|
file l_file : TEXT;
|
file con_file : TEXT) is
|
file con_file : TEXT) is
|
|
|
begin
|
begin
|
|
|
-- 'Connect' all the internal signals we want to watch to members of
|
-- 'Connect' all the internal signals we want to watch to members of
|
-- the info record.
|
-- the info record.
|
init_signal_spy(mcu& "/cpu/alu/"&"acc_input",iname&".acc_input", 0);
|
init_signal_spy(mcu& "/cpu/alu/"&"acc_input",iname&".acc_input", 0);
|
init_signal_spy(mcu& "/cpu/alu/"&"load_acc", iname&".load_acc", 0);
|
init_signal_spy(mcu& "/cpu/alu/"&"load_acc", iname&".load_acc", 0);
|
init_signal_spy(mcu& "/cpu/update_sp", iname&".update_sp", 0);
|
init_signal_spy(mcu& "/cpu/update_sp", iname&".update_sp", 0);
|
init_signal_spy(mcu& "/cpu/SP_reg", iname&".sp", 0);
|
init_signal_spy(mcu& "/cpu/SP_reg", iname&".sp", 0);
|
init_signal_spy(mcu& "/cpu/"&"psw", iname&".psw", 0);
|
init_signal_spy(mcu& "/cpu/"&"psw", iname&".psw", 0);
|
init_signal_spy(mcu& "/cpu/"&"update_psw_flags",iname&".update_psw_flags(0)", 0);
|
init_signal_spy(mcu& "/cpu/"&"update_psw_flags",iname&".update_psw_flags(0)", 0);
|
init_signal_spy(mcu& "/cpu/"&"code_addr", iname&".code_addr", 0);
|
init_signal_spy(mcu& "/cpu/"&"code_addr", iname&".code_addr", 0);
|
init_signal_spy(mcu& "/cpu/"&"ps", iname&".ps", 0);
|
init_signal_spy(mcu& "/cpu/"&"ps", iname&".ps", 0);
|
|
init_signal_spy(mcu& "/cpu/"&"jump_condition", iname&".jump_condition", 0);
|
|
init_signal_spy(mcu& "/cpu/"&"rel_jump_target", iname&".rel_jump_target", 0);
|
init_signal_spy(mcu& "/cpu/"&"bram_we", iname&".bram_we", 0);
|
init_signal_spy(mcu& "/cpu/"&"bram_we", iname&".bram_we", 0);
|
init_signal_spy(mcu& "/cpu/"&"bram_addr_p0", iname&".bram_wr_addr", 0);
|
init_signal_spy(mcu& "/cpu/"&"bram_addr_p0", iname&".bram_wr_addr", 0);
|
init_signal_spy(mcu& "/cpu/"&"bram_wr_data_p0", iname&".bram_wr_data_p0", 0);
|
init_signal_spy(mcu& "/cpu/"&"bram_wr_data_p0", iname&".bram_wr_data_p0", 0);
|
init_signal_spy(mcu& "/cpu/"&"next_pc", iname&".next_pc", 0);
|
init_signal_spy(mcu& "/cpu/"&"next_pc", iname&".next_pc", 0);
|
init_signal_spy(mcu& "/cpu/"&"sfr_we", iname&".sfr_we", 0);
|
init_signal_spy(mcu& "/cpu/"&"sfr_we", iname&".sfr_we", 0);
|
init_signal_spy(mcu& "/cpu/"&"sfr_wr", iname&".sfr_wr", 0);
|
init_signal_spy(mcu& "/cpu/"&"sfr_wr", iname&".sfr_wr", 0);
|
init_signal_spy(mcu& "/cpu/"&"sfr_addr", iname&".sfr_addr", 0);
|
init_signal_spy(mcu& "/cpu/"&"sfr_addr", iname&".sfr_addr", 0);
|
init_signal_spy(mcu& "/cpu/"&"inc_dptr", iname&".inc_dptr", 0);
|
init_signal_spy(mcu& "/cpu/"&"inc_dptr", iname&".inc_dptr", 0);
|
init_signal_spy(mcu& "/cpu/"&"DPTR_reg", iname&".dptr", 0);
|
init_signal_spy(mcu& "/cpu/"&"DPTR_reg", iname&".dptr", 0);
|
init_signal_spy(mcu& "/"&"xdata_we", iname&".xdata_we", 0);
|
init_signal_spy(mcu& "/"&"xdata_we", iname&".xdata_we", 0);
|
init_signal_spy(mcu& "/"&"xdata_vma", iname&".xdata_vma", 0);
|
init_signal_spy(mcu& "/"&"xdata_vma", iname&".xdata_vma", 0);
|
init_signal_spy(mcu& "/"&"xdata_addr", iname&".xdata_addr", 0);
|
init_signal_spy(mcu& "/"&"xdata_addr", iname&".xdata_addr", 0);
|
init_signal_spy(mcu& "/"&"xdata_wr", iname&".xdata_wr", 0);
|
init_signal_spy(mcu& "/"&"xdata_wr", iname&".xdata_wr", 0);
|
init_signal_spy(mcu& "/cpu/"&"code_rd", iname&".code_rd", 0);
|
init_signal_spy(mcu& "/cpu/"&"code_rd", iname&".code_rd", 0);
|
|
|
-- We force both 'rdy' uart outputs to speed up the simulation (since the
|
-- We force both 'rdy' uart outputs to speed up the simulation (since the
|
-- UART operation is not simulated by B51, just logged).
|
-- UART operation is not simulated by B51, just logged).
|
signal_force(mcu&"/uart/rx_rdy_flag", "1", 0 ms, freeze, -1 ms, 0);
|
signal_force(mcu&"/uart/rx_rdy_flag", "1", 0 ms, freeze, -1 ms, 0);
|
signal_force(mcu&"/uart/tx_busy", "0", 0 ms, freeze, -1 ms, 0);
|
signal_force(mcu&"/uart/tx_busy", "0", 0 ms, freeze, -1 ms, 0);
|
-- And we force the UART RX data to a predictable value until we implement
|
-- And we force the UART RX data to a predictable value until we implement
|
-- UART RX simulation in the B51 simulator, eventually.
|
-- UART RX simulation in the B51 simulator, eventually.
|
signal_force(mcu&"/uart/rx_buffer", "00000000", 0 ms, freeze, -1 ms, 0);
|
signal_force(mcu&"/uart/rx_buffer", "00000000", 0 ms, freeze, -1 ms, 0);
|
|
|
|
|
-- Initialize the console log line buffer...
|
-- Initialize the console log line buffer...
|
info.con_line_buf <= (others => ' ');
|
info.con_line_buf <= (others => ' ');
|
-- ...and take note of the ROM size
|
-- ...and take note of the ROM size
|
-- FIXME this should not be necessary, we know the array size already.
|
-- FIXME this should not be necessary, we know the array size already.
|
info.rom_size <= rom_size;
|
info.rom_size <= rom_size;
|
|
|
-- Initialize the observed cycle counting logic...
|
-- Initialize the observed cycle counting logic...
|
info.cycles <= (others => (999,0,0));
|
info.cycles <= (others => (999,0,0));
|
info.cycle_count <= 0;
|
info.cycle_count <= 0;
|
info.last_opcode <= "UUUUUUUU";
|
info.last_opcode <= "UUUUUUUU";
|
|
info.delayed_acc_log <= false;
|
|
|
-- ...and we're ready to start monitoring the system
|
-- ...and we're ready to start monitoring the system
|
while done='0' loop
|
while done='0' loop
|
wait until clk'event and clk='1';
|
wait until clk'event and clk='1';
|
if reset='1' then
|
if reset='1' then
|
-- Initialize some aux vars so as to avoid spurious 'diffs' upon
|
-- Initialize some aux vars so as to avoid spurious 'diffs' upon
|
-- reset.
|
-- reset.
|
info.pc <= X"0000";
|
info.pc <= X"0000";
|
info.psw_prev <= X"00";
|
info.psw_prev <= X"00";
|
info.sp_reg_prev <= X"07";
|
info.sp_reg_prev <= X"07";
|
info.a_reg_prev <= X"00";
|
info.a_reg_prev <= X"00";
|
|
|
-- Logging must be enabled from outside by setting
|
-- Logging must be enabled from outside by setting
|
-- log_trigger_address to a suitable value.
|
-- log_trigger_address to a suitable value.
|
info.log_trigger_address <= trigger_addr;
|
info.log_trigger_address <= trigger_addr;
|
info.log_triggered <= false;
|
info.log_triggered <= false;
|
|
|
info.con_line_ix <= 1; -- uart log line buffer is empty
|
info.con_line_ix <= 1; -- uart log line buffer is empty
|
else
|
else
|
log_cpu_status(info, l_file, con_file);
|
log_cpu_status(info, l_file, con_file);
|
end if;
|
end if;
|
end loop;
|
end loop;
|
|
|
-- Once finished, optionally log the cycle count table to a separate file.
|
-- Once finished, optionally log the cycle count table to a separate file.
|
log_cycle_counts(info);
|
log_cycle_counts(info);
|
|
|
end procedure log_cpu_activity;
|
end procedure log_cpu_activity;
|
|
|
|
|
|
|
procedure log_flush_console(
|
procedure log_flush_console(
|
signal info : in t_log_info;
|
signal info : in t_log_info;
|
file con_file : TEXT) is
|
file con_file : TEXT) is
|
variable l : line;
|
variable l : line;
|
begin
|
begin
|
-- If there's any character in the line buffer...
|
-- If there's any character in the line buffer...
|
if info.con_line_ix > 1 then
|
if info.con_line_ix > 1 then
|
-- ...then write the line buffer to the console log file.
|
-- ...then write the line buffer to the console log file.
|
write(l, info.con_line_buf(1 to info.con_line_ix));
|
write(l, info.con_line_buf(1 to info.con_line_ix));
|
writeline(con_file, l);
|
writeline(con_file, l);
|
end if;
|
end if;
|
end procedure log_flush_console;
|
end procedure log_flush_console;
|
|
|
procedure log_cycle_counts(
|
procedure log_cycle_counts(
|
signal info : in t_log_info) is
|
signal info : in t_log_info) is
|
variable cc : t_opcode_cycle_count;
|
variable cc : t_opcode_cycle_count;
|
variable opc : natural;
|
variable opc : natural;
|
file log_cycles_file: TEXT open write_mode is "cycle_count_log.csv";
|
file log_cycles_file: TEXT open write_mode is "cycle_count_log.csv";
|
begin
|
begin
|
|
|
for row in 0 to 15 loop
|
for row in 0 to 15 loop
|
for col in 0 to 15 loop
|
for col in 0 to 15 loop
|
opc := col*16 + row;
|
opc := col*16 + row;
|
cc := info.cycles(opc);
|
cc := info.cycles(opc);
|
print(log_cycles_file,
|
print(log_cycles_file,
|
""& hstr(to_unsigned(opc,8))& ","&
|
""& hstr(to_unsigned(opc,8))& ","&
|
str(cc.min)& ","& str(cc.max)& ","& str(cc.exe));
|
str(cc.min)& ","& str(cc.max)& ","& str(cc.exe));
|
end loop;
|
end loop;
|
end loop;
|
end loop;
|
|
|
end procedure log_cycle_counts;
|
end procedure log_cycle_counts;
|
|
|
|
|
end package body;
|
end package body;
|
|
|