//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// Project: light8080 SOC WiCores Solutions
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// Project: light8080 SOC WiCores Solutions
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//
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//
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// Filename: tb_l80soc.v (February 04, 2012)
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// Filename: tb_l80soc.v (February 04, 2012)
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//
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//
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// Author(s): Moti Litochevski
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// Author(s): Moti Litochevski
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//
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//
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// Description:
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// Description:
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// This file implements the light8080 SOC test bench.
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// This file implements the light8080 SOC test bench.
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//
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//
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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//
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//
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// To Do:
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// To Do:
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// -
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// -
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//
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//
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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//
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//
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// Copyright (C) 2012 Moti Litochevski
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// Copyright (C) 2012 Moti Litochevski
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//
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//
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// This source file may be used and distributed without restriction provided that this
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// This source file may be used and distributed without restriction provided that this
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// copyright statement is not removed from the file and that any derivative work
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// copyright statement is not removed from the file and that any derivative work
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// contains the original copyright notice and the associated disclaimer.
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// contains the original copyright notice and the associated disclaimer.
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//
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//
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// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES,
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// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
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// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
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// FITNESS FOR A PARTICULAR PURPOSE.
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// FITNESS FOR A PARTICULAR PURPOSE.
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//
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//
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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`timescale 1ns / 1ns
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`timescale 1ns / 1ns
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module test;
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module test;
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// test bench global defines
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// test bench global defines
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// the following define selects between CPU instruction trace and uart transmitted bytes
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// the following define selects between CPU instruction trace and uart transmitted bytes
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//`define CPU_TRACE 1
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//`define CPU_TRACE 1
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// internal signals
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// internal signals
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reg clock; // global clock
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reg clock; // global clock
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reg reset; // global reset
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reg reset; // global reset
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// UUT interfaces
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// UUT interfaces
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wire rxd, txd;
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wire rxd, txd;
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wire [7:0] p1dio, p2dio;
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wire [7:0] p1dio, p2dio;
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wire [3:0] extint;
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reg sp1dio0;
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// test bench implementation
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// test bench implementation
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// global signals generation
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// global signals generation
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initial
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initial
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begin
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begin
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clock = 0;
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clock = 0;
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reset = 1;
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reset = 1;
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#100 reset = 0;
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#100 reset = 0;
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end
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end
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// clock generator - 50MHz clock
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// clock generator - 50MHz clock
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always
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always
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begin
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begin
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#10 clock = 0;
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#10 clock = 0;
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#10 clock = 1;
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#10 clock = 1;
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end
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end
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// test bench dump variables
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// test bench dump variables
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initial
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initial
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begin
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begin
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$display("");
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$display("");
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$display(" light8080 SOC simulation");
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$display(" light8080 SOC simulation");
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$display("--------------------------------------");
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$display("--------------------------------------");
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$dumpfile("test.vcd");
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$dumpfile("test.vcd");
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$dumpvars(0, test);
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$dumpvars(0, test);
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$display("");
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$display("");
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end
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end
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// simulation end condition
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// simulation end condition
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always @ (posedge clock)
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always @ (posedge clock)
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begin
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begin
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if (dut.cpu_io && (dut.cpu_addr[7:0] == 8'hff))
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if (dut.cpu_io && (dut.cpu_addr[7:0] == 8'hff))
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begin
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begin
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$display("");
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$display("");
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$display("Simulation ended by software");
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$display("Simulation ended by software");
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$finish;
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$finish;
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end
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end
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end
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end
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// device under test
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// device under test
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l80soc dut
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l80soc dut
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(
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(
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.clock(clock),
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.clock(clock),
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.reset(reset),
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.reset(reset),
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.txd(txd),
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.txd(txd),
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.rxd(rxd),
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.rxd(rxd),
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.p1dio(p1dio),
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.p1dio(p1dio),
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.p2dio(p2dio)
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.p2dio(p2dio),
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.extint(extint)
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);
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);
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// uart receive is not used in this test becnch
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// uart receive is not used in this test becnch
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assign rxd = 1'b1;
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assign rxd = 1'b1;
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// external interrupt 0 is connected to the p1dio[0] rising edge
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assign extint[3:1] = 3'b0;
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assign extint[0] = ((sp1dio0 == 1'b0) && (p1dio[0] == 1'b1)) ? 1'b1 : 1'b0;
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// p1dio[0] rising edge detection
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always @ (posedge reset or posedge clock)
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begin
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if (reset)
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sp1dio0 <= 1'b0;
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else if (p1dio[0] == 1'b1)
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sp1dio0 <= 1'b1;
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else
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sp1dio0 <= 1'b0;
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end
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//------------------------------------------------------------------
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// test bench output log selection - either simple CPU trace or UART
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// transmit port log
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`ifdef CPU_TRACE
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`ifdef CPU_TRACE
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// display executed instructions
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// display executed instructions
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reg [15:0] saddr;
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reg [15:0] saddr;
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reg scpu_rd;
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reg scpu_rd;
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always @ (posedge clock)
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always @ (posedge clock)
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begin
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begin
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if (dut.cpu.uc_decode)
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if (dut.cpu.uc_decode)
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begin
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begin
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$display("");
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$display("");
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$write("%x : %x", saddr, dut.cpu.data_in);
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$write("%x : %x", saddr, dut.cpu.data_in);
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end
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end
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else if (scpu_rd)
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else if (scpu_rd)
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$write("%x", dut.cpu.data_in);
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$write("%x", dut.cpu.data_in);
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// sampled address bus and read pulse
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// sampled address bus and read pulse
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saddr <= dut.cpu.addr_out;
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saddr <= dut.cpu.addr_out;
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scpu_rd <= dut.cpu.rd;
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scpu_rd <= dut.cpu.rd;
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end
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end
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`else
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`else
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// display characters transmitted to the uart
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// display characters transmitted to the uart
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initial
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initial
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begin
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begin
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$display("Characters sent to the UART:");
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$display("Characters sent to the UART:");
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end
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end
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// check uart write pulse
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// check uart write pulse
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always @ (posedge clock)
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always @ (posedge clock)
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begin
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begin
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if (dut.txValid)
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if (dut.txValid)
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$write("%c", dut.cpu_dout);
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$write("%c", dut.cpu_dout);
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end
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end
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`endif
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`endif
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endmodule
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endmodule
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// Th.. Th.. Th.. Thats all folks !!!
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// Th.. Th.. Th.. Thats all folks !!!
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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