//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// Project: light8080 SOC WiCores Solutions
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// Project: light8080 SOC WiCores Solutions
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//
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//
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// File name: intr_ctrl.v (March 02, 2012)
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// File name: intr_ctrl.v (March 02, 2012)
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//
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//
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// Writer: Moti Litochevski
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// Writer: Moti Litochevski
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//
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//
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// Description:
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// Description:
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// This file contains the light8080 SOC interrupt controller. The controller
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// This file contains the light8080 SOC interrupt controller. The controller
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// supports 4 external interrupt requests with fixed interrupt vector addresses.
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// supports 4 external interrupt requests with fixed interrupt vector addresses.
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// The interrupt vectors code is implemented in the "intr_vec.h" file included in
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// The interrupt vectors code is implemented in the "intr_vec.h" file included in
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// the projects C directory.
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// the projects C directory.
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// Note that the controller clears the interrupt request after the CPU read the
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// Note that the controller clears the interrupt request after the CPU read the
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// interrupt vector.
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// interrupt vector.
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//
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//
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// Revision History:
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// Revision History:
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//
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//
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// Rev <revnumber> <Date> <owner>
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// Rev <revnumber> <Date> <owner>
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// <comment>
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// <comment>
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//
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//
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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//
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//
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// Copyright (C) 2012 Moti Litochevski
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// Copyright (C) 2012 Moti Litochevski
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//
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//
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// This source file may be used and distributed without restriction provided that this
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// This source file may be used and distributed without restriction provided that this
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// copyright statement is not removed from the file and that any derivative work
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// copyright statement is not removed from the file and that any derivative work
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// contains the original copyright notice and the associated disclaimer.
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// contains the original copyright notice and the associated disclaimer.
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//
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//
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// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES,
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// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
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// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
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// FITNESS FOR A PARTICULAR PURPOSE.
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// FITNESS FOR A PARTICULAR PURPOSE.
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//
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//
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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module intr_ctrl
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module intr_ctrl
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(
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(
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clock, reset,
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clock, reset,
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ext_intr, cpu_intr,
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ext_intr, cpu_intr,
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cpu_inte, cpu_inta,
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cpu_inte, cpu_inta,
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cpu_rd, cpu_inst,
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cpu_rd, cpu_inst,
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intr_ena
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intr_ena
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);
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);
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// module interfaces
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// module interfaces
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// global signals
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// global signals
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input clock; // global clock input
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input clock; // global clock input
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input reset; // global reset input
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input reset; // global reset input
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// external interrupt sources
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// external interrupt sources
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// least significant bit has the highest priority, most significant bit has the lowest
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// least significant bit has the highest priority, most significant bit has the lowest
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// priority.
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// priority.
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input [3:0] ext_intr; // active high
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input [3:0] ext_intr; // active high
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// CPU interface
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// CPU interface
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output cpu_intr; // CPU interrupt request
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output cpu_intr; // CPU interrupt request
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input cpu_inte; // CPU interrupt enable - just to mask
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input cpu_inte; // CPU interrupt enable - just to mask
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input cpu_inta; // CPU interrupt acknowledge
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input cpu_inta; // CPU interrupt acknowledge
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input cpu_rd; // CPU read signal
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input cpu_rd; // CPU read signal
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output [7:0] cpu_inst; // interrupt calling instruction
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output [7:0] cpu_inst; // interrupt calling instruction
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// interrupt enable register
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// interrupt enable register
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input [3:0] intr_ena; // set high to enable respective interrupt
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input [3:0] intr_ena; // set high to enable respective interrupt
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// 8080 assembly code constants
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// 8080 assembly code constants
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// call instruction opcode used to call interrupt routine
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// RST instruction opcode used to call interrupt routines at addresses
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`define CALL_INST 8'hcd
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// int0: 0x08 / int1: 0x18 / int2: 0x28 / int3: 0x38
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// interrupt vectors fixed addresses - high address byte is 0
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`define RST_1_INST 8'hcf
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`define INT0_VEC 8'h08
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`define RST_3_INST 8'hdf
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`define INT1_VEC 8'h18
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`define RST_5_INST 8'hef
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`define INT2_VEC 8'h28
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`define RST_7_INST 8'hff
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`define INT3_VEC 8'h38
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// internal declarations
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// internal declarations
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// registered output
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// registered output
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reg [7:0] cpu_inst;
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reg [7:0] cpu_inst;
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// internals
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// internals
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reg [1:0] intSq, intSel;
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reg [1:0] intSq, intSel;
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reg [3:0] act_int, int_clr;
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reg [3:0] act_int, int_clr;
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reg [7:0] int_vec;
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reg [7:0] int_vec;
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// module implementation
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// module implementation
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// main interrupt controller control process
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// main interrupt controller control process
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always @ (posedge reset or posedge clock)
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always @ (posedge reset or posedge clock)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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intSq <= 2'b0;
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intSq <= 2'b0;
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intSel <= 2'b0;
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intSel <= 2'b0;
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cpu_inst <= 8'b0;
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cpu_inst <= 8'b0;
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end
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end
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else
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else
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begin
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begin
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// interrupt controller state machine
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// interrupt controller state machine
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case (intSq)
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case (intSq)
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2'd0: // idle state - wait for active interrupt
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2'd0: // idle state - wait for active interrupt
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if ((act_int != 4'b0) && cpu_inte)
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if ((act_int != 4'b0) && cpu_inte)
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begin
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begin
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// latch the index of the active interrupt according to priority
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// latch the index of the active interrupt according to priority
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if (act_int[0]) intSel <= 2'd0;
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if (act_int[0]) intSel <= 2'd0;
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else if (act_int[2]) intSel <= 2'd1;
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else if (act_int[2]) intSel <= 2'd1;
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else if (act_int[3]) intSel <= 2'd2;
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else if (act_int[3]) intSel <= 2'd2;
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else intSel <= 2'd3;
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else intSel <= 2'd3;
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// switch to next state
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// switch to next state
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intSq <= 2'd1;
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intSq <= 2'd1;
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end
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end
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default: // all other states increment the state register on inta read
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2'd1: // wait for inta read cycle
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if (cpu_inta && cpu_rd)
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if (cpu_inta && cpu_rd)
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begin
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begin
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// update state
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// update instruction opcode
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intSq <= intSq + 1;
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cpu_inst <= int_vec;
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// switch to end for inta release
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// update instruction opcode for each byte read during inta
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intSq <= 2'd2;
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case (intSq)
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2'd1: cpu_inst <= `CALL_INST;
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2'd2: cpu_inst <= int_vec;
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default: cpu_inst <= 8'd0;
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endcase
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end
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end
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else if (!cpu_inta)
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default: // wait for inta end
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if (!cpu_inta)
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begin
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begin
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intSq <= 2'd0;
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// reset state machine
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cpu_inst <= 8'd0;
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intSq <= 2'b0;
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cpu_inst <= 8'b0;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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// assign interrupt vector address according to selected interrupt
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// assign interrupt vector address according to selected interrupt
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always @ (intSel)
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always @ (intSel)
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begin
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begin
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case (intSel)
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case (intSel)
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2'd0: int_vec <= `INT0_VEC;
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2'd0: int_vec <= `RST_1_INST;
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2'd1: int_vec <= `INT1_VEC;
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2'd1: int_vec <= `RST_3_INST;
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2'd2: int_vec <= `INT2_VEC;
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2'd2: int_vec <= `RST_5_INST;
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2'd3: int_vec <= `INT3_VEC;
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2'd3: int_vec <= `RST_7_INST;
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endcase
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endcase
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end
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end
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// latch active interrupt on rising edge
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// latch active interrupt on rising edge
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always @ (posedge reset or posedge clock)
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always @ (posedge reset or posedge clock)
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begin
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begin
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if (reset)
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if (reset)
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act_int <= 4'b0;
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act_int <= 4'b0;
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else
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else
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act_int <= (act_int & ~int_clr) | (ext_intr & intr_ena);
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act_int <= (act_int & ~int_clr) | (ext_intr & intr_ena);
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end
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end
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// CPU interrupt is asserted when at least one interrupt is active
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// CPU interrupt is asserted when at least one interrupt is active
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assign cpu_intr = |act_int;
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assign cpu_intr = |act_int;
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// clear serviced interrupt
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// clear serviced interrupt
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always @ (cpu_inta or cpu_rd or intSq or intSel)
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always @ (cpu_inta or cpu_rd or intSq or intSel)
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begin
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begin
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if (cpu_inta && cpu_rd && (intSq == 2'd3))
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if (cpu_inta && cpu_rd && (intSq == 2'd1))
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begin
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begin
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case (intSel)
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case (intSel)
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2'd0: int_clr <= 4'b0001;
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2'd0: int_clr <= 4'b0001;
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2'd1: int_clr <= 4'b0010;
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2'd1: int_clr <= 4'b0010;
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2'd2: int_clr <= 4'b0100;
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2'd2: int_clr <= 4'b0100;
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2'd3: int_clr <= 4'b1000;
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2'd3: int_clr <= 4'b1000;
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endcase
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endcase
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end
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end
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else
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else
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int_clr <= 4'b0;
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int_clr <= 4'b0;
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end
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end
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endmodule
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endmodule
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// Th.. Th.. Th.. Thats all folks !!!
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// Th.. Th.. Th.. Thats all folks !!!
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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