//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// Project: light8080 SOC WiCores Solutions
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// Project: light8080 SOC WiCores Solutions
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//
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//
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// File name: l80soc.v (February 04, 2012)
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// File name: l80soc.v (February 04, 2012)
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//
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//
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// Writer: Moti Litochevski
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// Writer: Moti Litochevski
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//
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//
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// Description:
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// Description:
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// This file contains the light8080 System On a Chip (SOC). the system includes the
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// This file contains the light8080 System On a Chip (SOC). the system includes the
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// CPU, program and data RAM and a UART interface and a general purpose digital IO.
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// CPU, program and data RAM and a UART interface and a general purpose digital IO.
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//
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//
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// Revision History:
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// Revision History:
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//
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//
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// Rev <revnumber> <Date> <owner>
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// Rev <revnumber> <Date> <owner>
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// <comment>
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// <comment>
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//
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//
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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//
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//
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// Copyright (C) 2012 Moti Litochevski
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// Copyright (C) 2012 Moti Litochevski
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//
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//
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// This source file may be used and distributed without restriction provided that this
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// This source file may be used and distributed without restriction provided that this
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// copyright statement is not removed from the file and that any derivative work
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// copyright statement is not removed from the file and that any derivative work
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// contains the original copyright notice and the associated disclaimer.
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// contains the original copyright notice and the associated disclaimer.
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//
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//
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// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES,
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// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
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// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
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// FITNESS FOR A PARTICULAR PURPOSE.
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// FITNESS FOR A PARTICULAR PURPOSE.
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//
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//
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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module l80soc
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module l80soc
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(
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(
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clock, reset,
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clock, reset,
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txd, rxd,
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txd, rxd,
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p1dio, p2dio
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p1dio, p2dio,
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extint
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);
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);
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// module interfaces
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// module interfaces
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// global signals
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// global signals
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input clock; // global clock input
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input clock; // global clock input
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input reset; // global reset input
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input reset; // global reset input
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// uart serial signals
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// uart serial signals
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output txd; // serial data output
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output txd; // serial data output
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input rxd; // serial data input
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input rxd; // serial data input
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// digital IO ports
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// digital IO ports
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inout [7:0] p1dio; // port 1 digital IO
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inout [7:0] p1dio; // port 1 digital IO
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inout [7:0] p2dio; // port 2 digital IO
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inout [7:0] p2dio; // port 2 digital IO
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// external interrupt sources
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input [3:0] extint; // external interrupt sources
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// io space registers addresses
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// io space registers addresses
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// uart registers
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// uart registers
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`define UDATA_REG 8'h80 // used for both transmit and receive
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`define UDATA_REG 8'h80 // used for both transmit and receive
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`define UBAUDL_REG 8'h81 // low byte of baud rate register
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`define UBAUDL_REG 8'h81 // low byte of baud rate register
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`define UBAUDH_REG 8'h82 // low byte of baud rate register
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`define UBAUDH_REG 8'h82 // low byte of baud rate register
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`define USTAT_REG 8'h83 // uart status register
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`define USTAT_REG 8'h83 // uart status register
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// dio port registers
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// dio port registers
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`define P1_DATA_REG 8'h84 // port 1 data register
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`define P1_DATA_REG 8'h84 // port 1 data register
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`define P1_DIR_REG 8'h85 // port 1 direction register
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`define P1_DIR_REG 8'h85 // port 1 direction register
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`define P2_DATA_REG 8'h86 // port 2 data register
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`define P2_DATA_REG 8'h86 // port 2 data register
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`define P2_DIR_REG 8'h87 // port 2 direction register
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`define P2_DIR_REG 8'h87 // port 2 direction register
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// interrupt controller register
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`define INTR_EN_REG 8'h88 // interrupts enable register
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// internal declarations
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// internal declarations
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// registered output
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// registered output
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// internals
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// internals
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wire [15:0] cpu_addr;
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wire [15:0] cpu_addr;
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wire [7:0] cpu_din, cpu_dout, ram_dout;
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wire [7:0] cpu_din, cpu_dout, ram_dout, intr_dout;
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wire cpu_io, cpu_rd, cpu_wr;
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wire cpu_io, cpu_rd, cpu_wr, cpu_inta, cpu_inte, cpu_intr;
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wire [7:0] txData;
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wire [7:0] txData, rxData;
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wire txValid, txBusy, rxValid, lcd_clk;
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wire txValid, txBusy, rxValid;
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wire [7:0] rxData;
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reg [15:0] uartbaud;
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reg [15:0] uartbaud;
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reg rxfull, scpu_io;
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reg rxfull, scpu_io;
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reg [7:0] p1reg, p1dir, p2reg, p2dir, io_dout;
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reg [7:0] p1reg, p1dir, p2reg, p2dir, io_dout;
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reg [3:0] intr_ena;
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// module implementation
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// module implementation
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// light8080 CPU instance
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// light8080 CPU instance
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light8080 cpu
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light8080 cpu
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(
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(
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.clk(clock),
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.clk(clock),
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.reset(reset),
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.reset(reset),
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.addr_out(cpu_addr),
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.addr_out(cpu_addr),
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.vma(/* nu */),
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.vma(/* nu */),
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.io(cpu_io),
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.io(cpu_io),
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.rd(cpu_rd),
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.rd(cpu_rd),
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.wr(cpu_wr),
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.wr(cpu_wr),
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.fetch(/* nu */),
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.fetch(/* nu */),
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.data_in(cpu_din),
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.data_in(cpu_din),
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.data_out(cpu_dout),
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.data_out(cpu_dout),
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.inta(/* nu */),
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.inta(cpu_inta),
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.inte(/* nu */),
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.inte(cpu_inte),
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.halt(/* nu */),
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.halt(/* nu */),
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.intr(1'b0)
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.intr(cpu_intr)
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);
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);
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// cpu data input selection
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// cpu data input selection
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assign cpu_din = scpu_io ? io_dout : ram_dout;
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assign cpu_din = (cpu_inta) ? intr_dout : (scpu_io) ? io_dout : ram_dout;
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// program and data Xilinx RAM memory
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// program and data Xilinx RAM memory
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ram_image ram
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ram_image ram
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(
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(
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.clk(clock),
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.clk(clock),
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.addr(cpu_addr[11:0]),
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.addr(cpu_addr[11:0]),
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.we(cpu_wr & ~cpu_io),
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.we(cpu_wr & ~cpu_io),
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.din(cpu_dout),
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.din(cpu_dout),
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.dout(ram_dout)
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.dout(ram_dout)
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);
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);
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// io space write registers
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// io space write registers
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always @ (posedge reset or posedge clock)
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always @ (posedge reset or posedge clock)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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uartbaud <= 16'b0;
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uartbaud <= 16'b0;
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rxfull <= 1'b0;
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rxfull <= 1'b0;
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p1reg <= 8'b0;
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p1reg <= 8'b0;
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p1dir <= 8'b0;
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p1dir <= 8'b0;
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p2reg <= 8'b0;
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p2reg <= 8'b0;
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p2dir <= 8'b0;
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p2dir <= 8'b0;
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intr_ena <= 4'b0;
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end
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end
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else
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else
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begin
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begin
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// io space registers
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// io space registers
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if (cpu_wr && cpu_io)
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if (cpu_wr && cpu_io)
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begin
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begin
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if (cpu_addr[7:0] == `UBAUDL_REG) uartbaud[7:0] <= cpu_dout;
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if (cpu_addr[7:0] == `UBAUDL_REG) uartbaud[7:0] <= cpu_dout;
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if (cpu_addr[7:0] == `UBAUDH_REG) uartbaud[15:8] <= cpu_dout;
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if (cpu_addr[7:0] == `UBAUDH_REG) uartbaud[15:8] <= cpu_dout;
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if (cpu_addr[7:0] == `P1_DATA_REG) p1reg <= cpu_dout;
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if (cpu_addr[7:0] == `P1_DATA_REG) p1reg <= cpu_dout;
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if (cpu_addr[7:0] == `P1_DIR_REG) p1dir <= cpu_dout;
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if (cpu_addr[7:0] == `P1_DIR_REG) p1dir <= cpu_dout;
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if (cpu_addr[7:0] == `P2_DATA_REG) p2reg <= cpu_dout;
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if (cpu_addr[7:0] == `P2_DATA_REG) p2reg <= cpu_dout;
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if (cpu_addr[7:0] == `P2_DIR_REG) p2dir <= cpu_dout;
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if (cpu_addr[7:0] == `P2_DIR_REG) p2dir <= cpu_dout;
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if (cpu_addr[7:0] == `INTR_EN_REG) intr_ena <= cpu_dout[3:0];
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end
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end
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// receiver full flag
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// receiver full flag
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if (rxValid && !rxfull)
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if (rxValid && !rxfull)
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rxfull <= 1'b1;
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rxfull <= 1'b1;
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else if (cpu_rd && cpu_io && (cpu_addr[7:0] == `UDATA_REG) && rxfull)
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else if (cpu_rd && cpu_io && (cpu_addr[7:0] == `UDATA_REG) && rxfull)
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rxfull <= 1'b0;
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rxfull <= 1'b0;
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end
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end
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end
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end
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// uart transmit write pulse
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// uart transmit write pulse
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assign txValid = cpu_wr & cpu_io & (cpu_addr[7:0] == `UDATA_REG);
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assign txValid = cpu_wr & cpu_io & (cpu_addr[7:0] == `UDATA_REG);
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// io space read registers
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// io space read registers
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always @ (posedge reset or posedge clock)
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always @ (posedge reset or posedge clock)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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io_dout <= 8'b0;
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io_dout <= 8'b0;
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end
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end
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else
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else
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begin
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begin
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// io space read registers
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// io space read registers
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if (cpu_io && (cpu_addr[7:0] == `UDATA_REG))
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if (cpu_io && (cpu_addr[7:0] == `UDATA_REG))
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io_dout <= rxData;
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io_dout <= rxData;
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else if (cpu_io && (cpu_addr[7:0] == `USTAT_REG))
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else if (cpu_io && (cpu_addr[7:0] == `USTAT_REG))
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io_dout <= {3'b0, rxfull, 3'b0, txBusy};
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io_dout <= {3'b0, rxfull, 3'b0, txBusy};
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else if (cpu_io && (cpu_addr[7:0] == `P1_DATA_REG))
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else if (cpu_io && (cpu_addr[7:0] == `P1_DATA_REG))
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io_dout <= p1dio;
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io_dout <= p1dio;
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else if (cpu_io && (cpu_addr[7:0] == `P2_DATA_REG))
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else if (cpu_io && (cpu_addr[7:0] == `P2_DATA_REG))
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io_dout <= p2dio;
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io_dout <= p2dio;
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// sampled io control to select cpu data input
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// sampled io control to select cpu data input
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scpu_io <= cpu_io;
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scpu_io <= cpu_io;
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end
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end
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end
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end
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// interrupt controller
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intr_ctrl intrc
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(
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.clock(clock),
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.reset(reset),
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.ext_intr(extint),
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.cpu_intr(cpu_intr),
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.cpu_inte(cpu_inte),
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.cpu_inta(cpu_inta),
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.cpu_rd(cpu_rd),
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.cpu_inst(intr_dout),
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.intr_ena(intr_ena)
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);
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// uart module mapped to the io space
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// uart module mapped to the io space
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uart uart
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uart uart
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(
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(
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.clock(clock),
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.clock(clock),
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.reset(reset),
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.reset(reset),
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.serIn(rxd),
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.serIn(rxd),
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.serOut(txd),
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.serOut(txd),
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.txData(cpu_dout),
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.txData(cpu_dout),
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.txValid(txValid),
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.txValid(txValid),
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.txBusy(txBusy),
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.txBusy(txBusy),
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.txDone(/* nu */),
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.txDone(/* nu */),
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.rxData(rxData),
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.rxData(rxData),
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.rxValid(rxValid),
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.rxValid(rxValid),
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.baudDiv(uartbaud)
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.baudDiv(uartbaud)
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);
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);
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// digital IO ports
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// digital IO ports
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// port 1
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// port 1
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assign p1dio[0] = p1dir[0] ? p1reg[0] : 1'bz;
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assign p1dio[0] = p1dir[0] ? p1reg[0] : 1'bz;
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assign p1dio[1] = p1dir[1] ? p1reg[1] : 1'bz;
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assign p1dio[1] = p1dir[1] ? p1reg[1] : 1'bz;
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assign p1dio[2] = p1dir[2] ? p1reg[2] : 1'bz;
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assign p1dio[2] = p1dir[2] ? p1reg[2] : 1'bz;
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assign p1dio[3] = p1dir[3] ? p1reg[3] : 1'bz;
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assign p1dio[3] = p1dir[3] ? p1reg[3] : 1'bz;
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assign p1dio[4] = p1dir[4] ? p1reg[4] : 1'bz;
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assign p1dio[4] = p1dir[4] ? p1reg[4] : 1'bz;
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assign p1dio[5] = p1dir[5] ? p1reg[5] : 1'bz;
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assign p1dio[5] = p1dir[5] ? p1reg[5] : 1'bz;
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assign p1dio[6] = p1dir[6] ? p1reg[6] : 1'bz;
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assign p1dio[6] = p1dir[6] ? p1reg[6] : 1'bz;
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assign p1dio[7] = p1dir[7] ? p1reg[7] : 1'bz;
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assign p1dio[7] = p1dir[7] ? p1reg[7] : 1'bz;
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// port 2
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// port 2
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assign p2dio[0] = p2dir[0] ? p2reg[0] : 1'bz;
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assign p2dio[0] = p2dir[0] ? p2reg[0] : 1'bz;
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assign p2dio[1] = p2dir[1] ? p2reg[1] : 1'bz;
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assign p2dio[1] = p2dir[1] ? p2reg[1] : 1'bz;
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assign p2dio[2] = p2dir[2] ? p2reg[2] : 1'bz;
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assign p2dio[2] = p2dir[2] ? p2reg[2] : 1'bz;
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assign p2dio[3] = p2dir[3] ? p2reg[3] : 1'bz;
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assign p2dio[3] = p2dir[3] ? p2reg[3] : 1'bz;
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assign p2dio[4] = p2dir[4] ? p2reg[4] : 1'bz;
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assign p2dio[4] = p2dir[4] ? p2reg[4] : 1'bz;
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assign p2dio[5] = p2dir[5] ? p2reg[5] : 1'bz;
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assign p2dio[5] = p2dir[5] ? p2reg[5] : 1'bz;
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assign p2dio[6] = p2dir[6] ? p2reg[6] : 1'bz;
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assign p2dio[6] = p2dir[6] ? p2reg[6] : 1'bz;
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assign p2dio[7] = p2dir[7] ? p2reg[7] : 1'bz;
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assign p2dio[7] = p2dir[7] ? p2reg[7] : 1'bz;
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endmodule
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endmodule
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// Th.. Th.. Th.. Thats all folks !!!
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// Th.. Th.. Th.. Thats all folks !!!
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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