--##############################################################################
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--##############################################################################
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-- l80soc : light8080 SOC
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-- l80soc : light8080 SOC
|
--##############################################################################
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--##############################################################################
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-- v1.0 (27 mar 2012) First release. Jose A. Ruiz.
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-- v1.0 (27 mar 2012) First release. Jose A. Ruiz.
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-- v2.0 (16 apr 2012) Made interface a bit more useable, added comments.
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--
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-- This SoC is meant as an usage example for the light8080 core. The code shows
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-- how to interface the core to internal BRAM and other modules.
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-- This module is not meant to be used in real applications though it can be
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-- used as the starting point for one.
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--
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-- Please see the comments below for usage instructions.
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--
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--
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-- This file and all the light8080 project files are freeware (See COPYING.TXT)
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-- This file and all the light8080 project files are freeware (See COPYING.TXT)
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--##############################################################################
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--##############################################################################
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-- (See timing diagrams at bottom of file. More comprehensive explainations can
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-- be found in the design notes)
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--##############################################################################
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.l80pkg.all;
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use work.l80pkg.all;
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--##############################################################################
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--##############################################################################
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-- Interface pins:
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------------------
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-- p1in : Input port P1.
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-- p2out : Output port P2.
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-- rxd : UART RxD pin.
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-- txd : UART TxD pin.
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-- extint : External interrupt inputs, wired straight to the irq controller.
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-- EXCEPT for the one used by the UART -- see generic UART_IRQ_LINE.
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-- clk : Master clock, rising edge active.
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-- reset : Synchronous reset, 1 cycle active to reset all SoC.
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--
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--------------------------------------------------------------------------------
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-- Generics:
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------------
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-- OBJ_CODE (mandatory, no default value):
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-- Table that will be used to initialize internal BRAM, starting at address 0.
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--
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-- DEFAULT_RAM_SIZE (default = 0):
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-- Internal RAM size. If set to zero, the RAM size will be determined from the
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-- size of OBJ_CODE as the smallest power of 2 larger than OBJ_CODE'length.
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--
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-- UART_IRQ_LINE (defaults to 4):
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-- Index of the irq controller input the internal UART is wired to, or >3 to
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-- leave the UART unconnected to the IRQ controller.
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-- The irq controller input used for the uart will be unconnected to the SoC
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-- input port.
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--
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-- UART_HARDWIRED (defaults to true):
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-- True when the UART baud rate is hardwired. the baud rate registers will be
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--
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-- BAUD_RATE (defaults to 19200):
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-- UART default baud rate. When th UART is hardwired, the baud rate can't be
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-- changed at run time.
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-- Note that you have to set generic z. This value is needed to compute the
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-- UART baud rate constants.
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--
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--
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--------------------------------------------------------------------------------
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-- I/O port map:
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----------------
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--
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-- 080h..083h UART registers.
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-- 084h P1 input port (read only, writes are ignored).
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-- 086h P2 output port (write only, reads undefined data).
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-- 088h IRQ enable register.
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--
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-- Please see the comments in the source of the relevant modules for a more
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-- detailed explanation of their behavior.
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--
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-- All i/o ports other than the above read as 00h.
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--------------------------------------------------------------------------------
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-- Notes:
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---------
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-- -# If you do not set a default memory size, you then have to take care to
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-- control the size of the object code table.
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-- -# If you do set the default memory size, the code will not warn you if the
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-- object code does not fit inside, it will silentl truncate it.
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-- -# The internal memory block is mirrored over the entire address map.
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-- -# There is no write protection to any address range: you can overwrite the
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-- program. If you do that there's no way to recover it but reloading the
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-- FPGA, a reset will not do.
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--##############################################################################
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--##############################################################################
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entity l80soc is
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entity l80soc is
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generic (
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generic (
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OBJ_CODE : obj_code_t; -- RAM initialization constant
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OBJ_CODE : obj_code_t; -- RAM initialization constant
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RAM_ADDR_SIZE : integer := 12; -- RAM address width
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DEFAULT_RAM_SIZE: integer := 0; -- RAM size or 0 to stretch
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UART_IRQ_LINE : integer := 4; -- [0..3] or >3 for none
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UART_IRQ_LINE : integer := 4; -- [0..3] or >3 for none
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UART_HARDWIRED: boolean := true; -- UART baud rate is hardwired
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UART_HARDWIRED: boolean := true; -- UART baud rate is hardwired
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BAUD_RATE : integer := 19200; -- UART (default) baud rate
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BAUD_RATE : integer := 19200; -- UART (default) baud rate
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CLOCK_FREQ : integer := 50E6 -- Clock frequency in Hz
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CLOCK_FREQ : integer := 50E6 -- Clock frequency in Hz
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);
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);
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port (
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port (
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p1in : in std_logic_vector(7 downto 0);
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p1in : in std_logic_vector(7 downto 0);
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p2out : out std_logic_vector(7 downto 0);
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p2out : out std_logic_vector(7 downto 0);
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rxd : in std_logic;
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rxd : in std_logic;
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txd : out std_logic;
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txd : out std_logic;
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extint : in std_logic_vector(3 downto 0);
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extint : in std_logic_vector(3 downto 0);
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic
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reset : in std_logic
|
);
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);
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end l80soc;
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end l80soc;
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--##############################################################################
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--##############################################################################
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--
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--
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--##############################################################################
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--##############################################################################
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architecture hardwired of l80soc is
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architecture hardwired of l80soc is
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-- Helper functions ------------------------------------------------------------
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-- soc_ram_size: compute size of internal RAM
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-- If default_size is /= 0, the size is the default. If it is zero, then the
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-- size the smallest power of 2 larger than obj_code_size.
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function soc_ram_size(default_size, obj_code_size: integer) return integer is
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begin
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if default_size=0 then
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-- Default is zero: use a RAM as big as necessary for the obj code table
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-- rounding to the neares power of 2.
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return 2**log2(obj_code_size);
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else
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-- Default is not zero: use the default and do NOT check to see if the
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-- object code fits.
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return default_size;
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end if;
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end function soc_ram_size;
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-- Custom types ----------------------------------------------------------------
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subtype t_byte is std_logic_vector(7 downto 0);
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subtype t_byte is std_logic_vector(7 downto 0);
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-- CPU signals -----------------------------------------------------------------
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-- CPU signals -----------------------------------------------------------------
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signal cpu_vma : std_logic;
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signal cpu_vma : std_logic;
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signal cpu_rd : std_logic;
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signal cpu_rd : std_logic;
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signal cpu_wr : std_logic;
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signal cpu_wr : std_logic;
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signal cpu_io : std_logic;
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signal cpu_io : std_logic;
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signal cpu_fetch : std_logic;
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signal cpu_fetch : std_logic;
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signal cpu_addr : std_logic_vector(15 downto 0);
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signal cpu_addr : std_logic_vector(15 downto 0);
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signal cpu_data_i : std_logic_vector(7 downto 0);
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signal cpu_data_i : std_logic_vector(7 downto 0);
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signal cpu_data_o : std_logic_vector(7 downto 0);
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signal cpu_data_o : std_logic_vector(7 downto 0);
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signal cpu_intr : std_logic;
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signal cpu_intr : std_logic;
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signal cpu_inte : std_logic;
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signal cpu_inte : std_logic;
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signal cpu_inta : std_logic;
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signal cpu_inta : std_logic;
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signal cpu_halt : std_logic;
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signal cpu_halt : std_logic;
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-- Aux CPU signals -------------------------------------------------------------
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-- Aux CPU signals -------------------------------------------------------------
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-- io_wr: asserted in IO write cycles
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-- io_wr: asserted in IO write cycles
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signal io_wr : std_logic;
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signal io_wr : std_logic;
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-- io_rd: asserted in IO read cycles
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-- io_rd: asserted in IO read cycles
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signal io_rd : std_logic;
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signal io_rd : std_logic;
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-- io_addr: IO port address, lowest 8 bits of address bus
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-- io_addr: IO port address, lowest 8 bits of address bus
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signal io_addr : std_logic_vector(7 downto 0);
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signal io_addr : std_logic_vector(7 downto 0);
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-- io_rd_data: data coming from IO ports (io input mux)
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-- io_rd_data: data coming from IO ports (io input mux)
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signal io_rd_data : std_logic_vector(7 downto 0);
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signal io_rd_data : std_logic_vector(7 downto 0);
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-- cpu_io_reg: registered cpu_io, used to control mux after cpu_io deasserts
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-- cpu_io_reg: registered cpu_io, used to control mux after cpu_io deasserts
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signal cpu_io_reg : std_logic;
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signal cpu_io_reg : std_logic;
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-- UART ------------------------------------------------------------------------
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-- UART ------------------------------------------------------------------------
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signal uart_ce : std_logic;
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signal uart_ce : std_logic;
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signal uart_data_rd : std_logic_vector(7 downto 0);
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signal uart_data_rd : std_logic_vector(7 downto 0);
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signal uart_irq : std_logic;
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signal uart_irq : std_logic;
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-- RAM -------------------------------------------------------------------------
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-- RAM -------------------------------------------------------------------------
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constant RAM_SIZE : integer := 4096;--2**RAM_ADDR_SIZE;
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constant RAM_SIZE : integer := soc_ram_size(DEFAULT_RAM_SIZE,OBJ_CODE'length);
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constant RAM_ADDR_SIZE : integer := log2(RAM_SIZE);
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signal ram_rd_data : std_logic_vector(7 downto 0);
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signal ram_rd_data : std_logic_vector(7 downto 0);
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signal ram_we : std_logic;
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signal ram_we : std_logic;
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signal ram : ram_t(0 to RAM_SIZE-1) := objcode_to_bram(OBJ_CODE, RAM_SIZE);
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signal ram : ram_t(0 to RAM_SIZE-1) := objcode_to_bram(OBJ_CODE, RAM_SIZE);
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signal ram_addr : std_logic_vector(RAM_ADDR_SIZE-1 downto 0);
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signal ram_addr : std_logic_vector(RAM_ADDR_SIZE-1 downto 0);
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-- IRQ controller interface ----------------------------------------------------
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-- IRQ controller interface ----------------------------------------------------
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signal irqcon_we : std_logic;
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signal irqcon_we : std_logic;
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signal irqcon_data_rd: std_logic_vector(7 downto 0);
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signal irqcon_data_rd: std_logic_vector(7 downto 0);
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signal irq : std_logic_vector(3 downto 0);
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signal irq : std_logic_vector(3 downto 0);
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-- IO ports addresses ----------------------------------------------------------
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-- IO ports addresses ----------------------------------------------------------
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subtype io_addr_t is std_logic_vector(7 downto 0);
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subtype io_addr_t is std_logic_vector(7 downto 0);
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constant ADDR_UART_0 : io_addr_t := X"80"; -- UART registers (80h..83h)
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constant ADDR_UART_0 : io_addr_t := X"80"; -- UART registers (80h..83h)
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constant ADDR_UART_1 : io_addr_t := X"81"; -- UART registers (80h..83h)
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constant ADDR_UART_1 : io_addr_t := X"81"; -- UART registers (80h..83h)
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constant ADDR_UART_2 : io_addr_t := X"82"; -- UART registers (80h..83h)
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constant ADDR_UART_2 : io_addr_t := X"82"; -- UART registers (80h..83h)
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constant ADDR_UART_3 : io_addr_t := X"83"; -- UART registers (80h..83h)
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constant ADDR_UART_3 : io_addr_t := X"83"; -- UART registers (80h..83h)
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constant P1_DATA_REG : io_addr_t := X"84"; -- port 1 data register
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constant P1_DATA_REG : io_addr_t := X"84"; -- port 1 data register
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constant P2_DATA_REG : io_addr_t := X"86"; -- port 2 data register
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constant P2_DATA_REG : io_addr_t := X"86"; -- port 2 data register
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constant INTR_EN_REG : io_addr_t := X"88"; -- interrupts enable register
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constant INTR_EN_REG : io_addr_t := X"88"; -- interrupts enable register
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|
|
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begin
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begin
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|
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cpu: entity work.light8080
|
cpu: entity work.light8080
|
port map (
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port map (
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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vma => cpu_vma,
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vma => cpu_vma,
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rd => cpu_rd,
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rd => cpu_rd,
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wr => cpu_wr,
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wr => cpu_wr,
|
io => cpu_io,
|
io => cpu_io,
|
fetch => cpu_fetch,
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fetch => cpu_fetch,
|
addr_out => cpu_addr,
|
addr_out => cpu_addr,
|
data_in => cpu_data_i,
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data_in => cpu_data_i,
|
data_out => cpu_data_o,
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data_out => cpu_data_o,
|
|
|
intr => cpu_intr,
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intr => cpu_intr,
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inte => cpu_inte,
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inte => cpu_inte,
|
inta => cpu_inta,
|
inta => cpu_inta,
|
halt => cpu_halt
|
halt => cpu_halt
|
);
|
);
|
|
|
io_rd <= cpu_io and cpu_rd;
|
io_rd <= cpu_io and cpu_rd;
|
io_wr <= '1' when cpu_io='1' and cpu_wr='1' else '0';
|
io_wr <= '1' when cpu_io='1' and cpu_wr='1' else '0';
|
io_addr <= cpu_addr(7 downto 0);
|
io_addr <= cpu_addr(7 downto 0);
|
|
|
-- Register some control signals that are needed to control multiplexors the
|
-- Register some control signals that are needed to control multiplexors the
|
-- cycle after the control signal asserts -- e.g. cpu_io.
|
-- cycle after the control signal asserts -- e.g. cpu_io.
|
control_signal_registers:
|
control_signal_registers:
|
process(clk)
|
process(clk)
|
begin
|
begin
|
if clk'event and clk='1' then
|
if clk'event and clk='1' then
|
cpu_io_reg <= cpu_io;
|
cpu_io_reg <= cpu_io;
|
end if;
|
end if;
|
end process control_signal_registers;
|
end process control_signal_registers;
|
|
|
-- Input data mux -- remember, no 3-state buses within the FPGA --------------
|
-- Input data mux -- remember, no 3-state buses within the FPGA --------------
|
cpu_data_i <=
|
cpu_data_i <=
|
irqcon_data_rd when cpu_inta = '1' else
|
irqcon_data_rd when cpu_inta = '1' else
|
io_rd_data when cpu_io_reg = '1' else
|
io_rd_data when cpu_io_reg = '1' else
|
ram_rd_data;
|
ram_rd_data;
|
|
|
|
|
-- BRAM ----------------------------------------------------------------------
|
-- BRAM ----------------------------------------------------------------------
|
|
|
ram_we <= '1' when cpu_io='0' and cpu_wr='1' else '0';
|
ram_we <= '1' when cpu_io='0' and cpu_wr='1' else '0';
|
ram_addr <= cpu_addr(RAM_ADDR_SIZE-1 downto 0);
|
ram_addr <= cpu_addr(RAM_ADDR_SIZE-1 downto 0);
|
|
|
memory:
|
memory:
|
process(clk)
|
process(clk)
|
begin
|
begin
|
if clk'event and clk='1' then
|
if clk'event and clk='1' then
|
if ram_we = '1' then
|
if ram_we = '1' then
|
ram(conv_integer(ram_addr)) <= cpu_data_o;
|
ram(conv_integer(ram_addr)) <= cpu_data_o;
|
end if;
|
end if;
|
ram_rd_data <= ram(conv_integer(ram_addr));
|
ram_rd_data <= ram(conv_integer(ram_addr));
|
end if;
|
end if;
|
end process memory;
|
end process memory;
|
|
|
|
|
-- Interrupt controller ------------------------------------------------------
|
-- Interrupt controller ------------------------------------------------------
|
-- FIXME interrupts unused in this version
|
-- FIXME interrupts unused in this version
|
|
|
irq_control: entity work.l80irq
|
irq_control: entity work.l80irq
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
|
|
|
irq_i => irq,
|
irq_i => irq,
|
|
|
data_i => cpu_data_o,
|
data_i => cpu_data_o,
|
data_o => irqcon_data_rd,
|
data_o => irqcon_data_rd,
|
addr_i => cpu_addr(0),
|
addr_i => cpu_addr(0),
|
data_we_i => irqcon_we,
|
data_we_i => irqcon_we,
|
|
|
cpu_inta_i => cpu_inta,
|
cpu_inta_i => cpu_inta,
|
cpu_intr_o => cpu_intr,
|
cpu_intr_o => cpu_intr,
|
cpu_fetch_i => cpu_fetch
|
cpu_fetch_i => cpu_fetch
|
);
|
);
|
|
|
irq_line_connections:
|
irq_line_connections:
|
for i in 0 to 3 generate
|
for i in 0 to 3 generate
|
begin
|
begin
|
uart_irq_connection:
|
uart_irq_connection:
|
if i = UART_IRQ_LINE generate
|
if i = UART_IRQ_LINE generate
|
begin
|
begin
|
irq(i) <= uart_irq;
|
irq(i) <= uart_irq;
|
end generate;
|
end generate;
|
other_irq_connections:
|
other_irq_connections:
|
if i /= UART_IRQ_LINE generate
|
if i /= UART_IRQ_LINE generate
|
irq(i) <= extint(i);
|
irq(i) <= extint(i);
|
end generate;
|
end generate;
|
end generate irq_line_connections;
|
end generate irq_line_connections;
|
|
|
irqcon_we <= '1' when io_addr=INTR_EN_REG and io_wr='1' else '0';
|
irqcon_we <= '1' when io_addr=INTR_EN_REG and io_wr='1' else '0';
|
|
|
-- UART -- simple UART with hardwired baud rate ------------------------------
|
-- UART -- simple UART with hardwired baud rate ------------------------------
|
-- NOTE: the serial port does NOT have interrupt capability (yet)
|
-- NOTE: the serial port does NOT have interrupt capability (yet)
|
|
|
uart : entity work.uart
|
uart : entity work.uart
|
generic map (
|
generic map (
|
BAUD_RATE => BAUD_RATE,
|
BAUD_RATE => BAUD_RATE,
|
CLOCK_FREQ => CLOCK_FREQ
|
CLOCK_FREQ => CLOCK_FREQ
|
)
|
)
|
port map (
|
port map (
|
clk_i => clk,
|
clk_i => clk,
|
reset_i => reset,
|
reset_i => reset,
|
|
|
irq_o => uart_irq,
|
irq_o => uart_irq,
|
data_i => cpu_data_o,
|
data_i => cpu_data_o,
|
data_o => uart_data_rd,
|
data_o => uart_data_rd,
|
addr_i => cpu_addr(1 downto 0),
|
addr_i => cpu_addr(1 downto 0),
|
|
|
ce_i => uart_ce,
|
ce_i => uart_ce,
|
wr_i => io_wr,
|
wr_i => io_wr,
|
rd_i => io_rd,
|
rd_i => io_rd,
|
|
|
rxd_i => rxd,
|
rxd_i => rxd,
|
txd_o => txd
|
txd_o => txd
|
);
|
);
|
|
|
-- UART write enable
|
-- UART write enable
|
uart_ce <= '1' when
|
uart_ce <= '1' when
|
io_addr(7 downto 2) = ADDR_UART_0(7 downto 2)
|
io_addr(7 downto 2) = ADDR_UART_0(7 downto 2)
|
else '0';
|
else '0';
|
|
|
-- IO ports -- Simple IO ports with hardcoded direction ----------------------
|
-- IO ports -- Simple IO ports with hardcoded direction ----------------------
|
-- These are meant as an usage example mostly
|
-- These are meant as an usage example mostly
|
|
|
output_ports:
|
output_ports:
|
process(clk)
|
process(clk)
|
begin
|
begin
|
if clk'event and clk='1' then
|
if clk'event and clk='1' then
|
if reset = '1' then
|
if reset = '1' then
|
-- Reset values for all io ports
|
-- Reset values for all io ports
|
p2out <= (others => '0');
|
p2out <= (others => '0');
|
else
|
else
|
if io_wr = '1' then
|
if io_wr = '1' then
|
if conv_integer(io_addr) = P2_DATA_REG then
|
if conv_integer(io_addr) = P2_DATA_REG then
|
p2out <= cpu_data_o;
|
p2out <= cpu_data_o;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process output_ports;
|
end process output_ports;
|
|
|
-- Input IO data multiplexor
|
-- Input IO data multiplexor
|
with io_addr select io_rd_data <=
|
with io_addr select io_rd_data <=
|
p1in when P1_DATA_REG,
|
p1in when P1_DATA_REG,
|
uart_data_rd when ADDR_UART_0,
|
uart_data_rd when ADDR_UART_0,
|
uart_data_rd when ADDR_UART_1,
|
uart_data_rd when ADDR_UART_1,
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uart_data_rd when ADDR_UART_2,
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uart_data_rd when ADDR_UART_2,
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uart_data_rd when ADDR_UART_3,
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uart_data_rd when ADDR_UART_3,
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irqcon_data_rd when INTR_EN_REG,
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irqcon_data_rd when INTR_EN_REG,
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X"00" when others;
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X"00" when others;
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|
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end hardwired;
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end hardwired;
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