--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Light8080 simulation test bench 1 : Interrupt response test
|
-- Light8080 simulation test bench 1 : Interrupt response test
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Source for the 8080 program is in asm\tb1.asm
|
-- Source for the 8080 program is in asm\tb1.asm
|
-- Upon completion, a value of 055h in ACC means success and a 0aah means
|
-- Upon completion, a value of 033h in ACC means success and a 0aah means
|
-- failure, but the proper behavior of intr/inta/halt has to be verified
|
-- failure, but the proper behavior of intr/inta/halt has to be verified
|
-- visually.
|
-- visually.
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
LIBRARY ieee;
|
LIBRARY ieee;
|
USE ieee.std_logic_1164.ALL;
|
USE ieee.std_logic_1164.ALL;
|
USE ieee.std_logic_unsigned.all;
|
USE ieee.std_logic_unsigned.all;
|
USE ieee.numeric_std.ALL;
|
USE ieee.numeric_std.ALL;
|
|
|
ENTITY light8080_tb1 IS
|
ENTITY light8080_tb1 IS
|
END light8080_tb1;
|
END light8080_tb1;
|
|
|
ARCHITECTURE behavior OF light8080_tb1 IS
|
ARCHITECTURE behavior OF light8080_tb1 IS
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Simulation parameters
|
-- Simulation parameters
|
|
|
-- T: simulation clock period
|
-- T: simulation clock period
|
constant T : time := 100 ns;
|
constant T : time := 100 ns;
|
|
|
-- sim_length: total simulation time
|
-- sim_length: total simulation time
|
constant sim_length : time := 45000 ns;
|
constant sim_length : time := 45000 ns;
|
|
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
-- Component Declaration for the Unit Under Test (UUT)
|
-- Component Declaration for the Unit Under Test (UUT)
|
COMPONENT light8080
|
COMPONENT light8080
|
PORT (
|
PORT (
|
addr_out : out std_logic_vector(15 downto 0);
|
addr_out : out std_logic_vector(15 downto 0);
|
|
|
inta : out std_logic;
|
inta : out std_logic;
|
inte : out std_logic;
|
inte : out std_logic;
|
halt : out std_logic;
|
halt : out std_logic;
|
intr : in std_logic;
|
intr : in std_logic;
|
|
|
vma : out std_logic;
|
vma : out std_logic;
|
io : out std_logic;
|
io : out std_logic;
|
rd : out std_logic;
|
rd : out std_logic;
|
wr : out std_logic;
|
wr : out std_logic;
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
|
|
clk : in std_logic;
|
clk : in std_logic;
|
reset : in std_logic );
|
reset : in std_logic );
|
END COMPONENT;
|
END COMPONENT;
|
|
|
|
|
SIGNAL data_i : std_logic_vector(7 downto 0) := (others=>'0');
|
SIGNAL data_i : std_logic_vector(7 downto 0) := (others=>'0');
|
|
|
SIGNAL vma_o : std_logic;
|
SIGNAL vma_o : std_logic;
|
SIGNAL rd_o : std_logic;
|
SIGNAL rd_o : std_logic;
|
SIGNAL wr_o : std_logic;
|
SIGNAL wr_o : std_logic;
|
SIGNAL io_o : std_logic;
|
SIGNAL io_o : std_logic;
|
SIGNAL data_o : std_logic_vector(7 downto 0);
|
SIGNAL data_o : std_logic_vector(7 downto 0);
|
SIGNAL data_mem : std_logic_vector(7 downto 0);
|
SIGNAL data_mem : std_logic_vector(7 downto 0);
|
SIGNAL addr_o : std_logic_vector(15 downto 0);
|
SIGNAL addr_o : std_logic_vector(15 downto 0);
|
|
|
signal inta_o : std_logic;
|
signal inta_o : std_logic;
|
signal inte_o : std_logic;
|
signal inte_o : std_logic;
|
signal intr_i : std_logic := '0';
|
signal intr_i : std_logic := '0';
|
signal halt_o : std_logic;
|
signal halt_o : std_logic;
|
|
|
signal reset : std_logic := '0';
|
signal reset : std_logic := '0';
|
signal clk : std_logic := '1';
|
signal clk : std_logic := '1';
|
signal done : std_logic := '0';
|
signal done : std_logic := '0';
|
|
|
type t_rom is array(0 to 2047) of std_logic_vector(7 downto 0);
|
type t_rom is array(0 to 2047) of std_logic_vector(7 downto 0);
|
|
|
signal rom : t_rom := (
|
signal rom : t_rom := (
|
|
|
X"c3",X"40",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"c3",X"40",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"c6",X"07",X"fb",X"c9",X"00",X"00",X"00",X"00",
|
X"c6",X"07",X"fb",X"c9",X"00",X"00",X"00",X"00",
|
X"47",X"c9",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"47",X"c9",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"31",X"06",X"02",X"fb",X"3e",X"00",X"ef",X"c6",
|
X"31",X"06",X"02",X"fb",X"3e",X"00",X"ef",X"c6",
|
X"01",X"c6",X"01",X"c6",X"01",X"c6",X"01",X"c6",
|
X"01",X"c6",X"01",X"c6",X"01",X"c6",X"01",X"c6",
|
X"01",X"c6",X"01",X"c6",X"01",X"fb",X"c6",X"01",
|
X"01",X"c6",X"01",X"c6",X"01",X"fb",X"c6",X"01",
|
X"c6",X"01",X"c6",X"01",X"fb",X"76",X"fe",X"11",
|
X"c6",X"01",X"c6",X"01",X"fb",X"76",X"fe",X"11",
|
X"c2",X"7b",X"00",X"78",X"fe",X"00",X"c2",X"7b",
|
X"c2",X"7b",X"00",X"78",X"fe",X"00",X"c2",X"7b",
|
X"00",X"79",X"fe",X"0c",X"c2",X"7b",X"00",X"7a",
|
X"00",X"79",X"fe",X"0c",X"c2",X"7b",X"00",X"7a",
|
X"fe",X"12",X"7b",X"fe",X"34",X"c2",X"7b",X"00",
|
X"fe",X"12",X"7b",X"fe",X"34",X"c2",X"7b",X"00",
|
X"3e",X"55",X"76",X"3e",X"aa",X"76",X"00",X"00",
|
X"3e",X"33",X"76",X"3e",X"aa",X"76",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"c6",X"09",X"06",X"77",X"fb",X"c9",X"00",X"00",
|
X"c6",X"09",X"06",X"77",X"fb",X"c9",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"
|
|
|
);
|
);
|
|
|
|
|
|
|
type t_int_vectors is array(0 to 15) of std_logic_vector(7 downto 0);
|
type t_int_vectors is array(0 to 15) of std_logic_vector(7 downto 0);
|
|
|
|
-- This ROM holds the int vectors that will be fed to the CPU along the test.
|
|
-- It will be read like a progrm ROM except a special pointer (vector_counter)
|
|
-- will be used instead of the PC (see below).
|
|
-- Of course this is a simulation trick not meant to be synthesized.
|
signal int_vectors : t_int_vectors := (
|
signal int_vectors : t_int_vectors := (
|
X"00", -- not used
|
X"00", -- not used (see below)
|
X"e7", -- rst 4 (rst 20h)
|
X"e7", -- rst 4 (rst 20h)
|
X"4f", -- mov c,a
|
X"4f", -- mov c,a
|
X"11", X"34", X"12", -- lxi d, 1234h
|
X"11", X"34", X"12", -- lxi d, 1234h
|
X"00", -- nop
|
X"00", -- nop
|
X"00", -- not used
|
X"00", -- not used
|
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"
|
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"
|
);
|
);
|
|
|
|
-- This will be used to read the irq vector ROM. It's a pointer that increments
|
|
-- whenever the CPU fetches a byte while inta_o is high.
|
signal vector_counter : integer := 0;
|
signal vector_counter : integer := 0;
|
|
-- Vector byte to be fed to the CPU in inta cycles
|
signal int_vector : std_logic_vector(7 downto 0);
|
signal int_vector : std_logic_vector(7 downto 0);
|
|
|
BEGIN
|
BEGIN
|
|
|
-- Instantiate the Unit Under Test (UUT)
|
-- Instantiate the Unit Under Test (UUT)
|
uut: light8080 PORT MAP(
|
uut: light8080 PORT MAP(
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
|
vma => vma_o,
|
vma => vma_o,
|
rd => rd_o,
|
rd => rd_o,
|
wr => wr_o,
|
wr => wr_o,
|
io => io_o,
|
io => io_o,
|
addr_out => addr_o,
|
addr_out => addr_o,
|
data_in => data_i,
|
data_in => data_i,
|
data_out => data_o,
|
data_out => data_o,
|
|
|
intr => intr_i,
|
intr => intr_i,
|
inte => inte_o,
|
inte => inte_o,
|
inta => inta_o,
|
inta => inta_o,
|
halt => halt_o
|
halt => halt_o
|
);
|
);
|
|
|
|
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
-- clock: Clocking process.
|
-- clock: Clocking process.
|
clock:
|
clock:
|
process(done, clk)
|
process(done, clk)
|
begin
|
begin
|
if done = '0' then
|
if done = '0' then
|
clk <= not clk after T/2;
|
clk <= not clk after T/2;
|
end if;
|
end if;
|
end process clock;
|
end process clock;
|
|
|
|
|
main_test:
|
main_test:
|
process
|
process
|
begin
|
begin
|
-- Assert reset for at least one full clk period
|
-- Assert reset for at least one full clk period
|
reset <= '1';
|
reset <= '1';
|
wait until clk = '1';
|
wait until clk = '1';
|
wait for T/2;
|
wait for T/2;
|
reset <= '0';
|
reset <= '0';
|
|
|
-- Remember to 'cut away' the preceding 3 clk semiperiods from
|
-- Remember to 'cut away' the preceding 3 clk semiperiods from
|
-- the wait statement...
|
-- the wait statement...
|
wait for (sim_length - T*1.5);
|
wait for (sim_length - T*1.5);
|
|
|
-- Stop the clk process asserting 'done'
|
-- Stop the clk process asserting 'done'
|
done <= '1';
|
done <= '1';
|
|
|
|
|
assert (done = '1')
|
assert (done = '1')
|
report "Test finished."
|
report "Test finished."
|
severity failure;
|
severity failure;
|
|
|
|
|
wait;
|
wait;
|
end process main_test;
|
end process main_test;
|
|
|
-- RAM access
|
-- (Code) RAM access
|
process(clk)
|
process(clk)
|
begin
|
begin
|
if (clk'event and clk='1') then
|
if (clk'event and clk='1') then
|
data_mem <= rom(conv_integer(addr_o(10 downto 0)));
|
data_mem <= rom(conv_integer(addr_o(10 downto 0)));
|
if wr_o = '1' then
|
if wr_o = '1' then
|
rom(conv_integer(addr_o(10 downto 0))) <= data_o;
|
rom(conv_integer(addr_o(10 downto 0))) <= data_o;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
-- Interrupt vector ROM pointer; update it whenever the CPU fetches a byte
|
|
-- while in INTA state.
|
process(clk)
|
process(clk)
|
begin
|
begin
|
if (clk'event and clk='1') then
|
if (clk'event and clk='1') then
|
if inta_o = '1' and vma_o = '1' and rd_o='1' then
|
if inta_o = '1' and vma_o = '1' and rd_o='1' then
|
vector_counter <= vector_counter + 1;
|
vector_counter <= vector_counter + 1;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
-- (Since the vector pointer pre-increments and the ROM in asynchronous, the
|
|
-- first byte of the ROM is never used).
|
int_vector <= int_vectors(vector_counter);
|
int_vector <= int_vectors(vector_counter);
|
|
|
data_i <= data_mem when inta_o='0' else int_vector;
|
data_i <= data_mem when inta_o='0' else int_vector;
|
|
|
|
-- Trigger the IRQ input in a pattern carefully synchronized to the code of
|
|
-- the test bench (see 'asm/tb1.asm').
|
int0:
|
int0:
|
process
|
process
|
begin
|
begin
|
intr_i <= '0';
|
intr_i <= '0';
|
|
|
--
|
--
|
wait for T*89;
|
wait for T*89;
|
intr_i <= '1';
|
intr_i <= '1';
|
wait for T;
|
wait for T;
|
intr_i <= '0';
|
intr_i <= '0';
|
|
|
--
|
--
|
wait for T*87;
|
wait for T*87;
|
intr_i <= '1';
|
intr_i <= '1';
|
wait for T;
|
wait for T;
|
intr_i <= '0';
|
intr_i <= '0';
|
|
|
--
|
--
|
wait for T*49;
|
wait for T*49;
|
intr_i <= '1';
|
intr_i <= '1';
|
wait for T;
|
wait for T;
|
intr_i <= '0';
|
intr_i <= '0';
|
|
|
-- intr after cpu is halted
|
-- intr after cpu is halted
|
wait for T*41;
|
wait for T*41;
|
intr_i <= '1';
|
intr_i <= '1';
|
wait for T;
|
wait for T;
|
intr_i <= '0';
|
intr_i <= '0';
|
|
|
wait;
|
wait;
|
end process int0;
|
end process int0;
|
|
|
END;
|
END;
|
|
|