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[/] [line_codes/] [trunk/] [bench/] [vhdl/] [smlt_hdb1_dec.vhd] - Diff between revs 2 and 8
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| Rev 2 |
Rev 8 |
-- smlttion for HDB1 decoder.
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-- smlttion for HDB1 decoder.
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entity smlt_hdb1_dec is
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entity smlt_hdb1_dec is
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end smlt_hdb1_dec;
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end smlt_hdb1_dec;
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architecture behaviour of smlt_hdb1_dec is
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architecture behaviour of smlt_hdb1_dec is
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--data type:
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--data type:
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component hdb1_dec
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component hdb1_dec
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port (
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port (
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clr_bar,
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clr_bar,
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clk, e0, e1 : in bit;
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clk, e0, e1 : in bit;
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s : out bit);
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s : out bit);
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end component;
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end component;
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--binding:
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--binding:
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for a: hdb1_dec use entity work.hdb1_dec;
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for a: hdb1_dec use entity work.hdb1_dec;
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--declaring the signals present in this architecture:
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--declaring the signals present in this architecture:
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signal CLK, S, E0, E1, clrb: bit;
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signal CLK, S, E0, E1, clrb: bit;
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signal input0, input1: bit_vector(0 to 24);
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signal input0, input1: bit_vector(0 to 24);
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begin --architecture.
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begin --architecture.
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a: hdb1_dec port map
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a: hdb1_dec port map
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( clr_bar => clrb, clk=> CLK, e0 => E0, e1 => E1,
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( clr_bar => clrb, clk=> CLK, e0 => E0, e1 => E1,
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s => S );
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s => S );
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input0 <= "0100010110001011001001101";
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input0 <= "0100010110001011001001101";
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input1 <= "0001001000100100100110010";
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input1 <= "0001001000100100100110010";
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process begin
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process begin
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clrb <= '1';
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clrb <= '1';
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for i in 0 to 24 loop
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for i in 0 to 24 loop
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E0 <= input0(i);
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E0 <= input0(i);
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E1 <= input1(i);
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E1 <= input1(i);
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CLK <= '0';
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CLK <= '0';
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wait for 9 ns;
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wait for 9 ns;
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CLK <= '1';
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CLK <= '1';
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wait for 1 ns;
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wait for 1 ns;
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end loop;
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end loop;
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wait;
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wait;
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end process;
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end process;
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end behaviour;
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end behaviour;
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