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/**************************************
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Author: J.W Tang
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Email: jaytang1987@hotmail.com
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Module: equivalence_resolver
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Date: 2016-04-24
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Copyright (C) 2016 J.W. Tang
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----------------------------
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This file is part of LinkRunCCA.
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LinkRunCCA is free software: you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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LinkRunCCA is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with LinkRunCCA. If not, see <http://www.gnu.org/licenses/>.
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By using LinkRunCCA in any or associated publication,
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you agree to cite it as:
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Tang, J. W., et al. "A linked list run-length-based single-pass
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connected component analysis for real-time embedded hardware."
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Journal of Real-Time Image Processing: 1-19. 2016.
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doi:10.1007/s11554-016-0590-2.
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***************************************/
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module equivalence_resolver(
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module equivalence_resolver(
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clk,rst,datavalid, //global input
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clk,rst,datavalid, //global input
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A,B,C,D,p,hp,np,tp,dp,fp,fn,dd, //input from other modules
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A,B,C,D,p,hp,np,tp,dp,fp,fn,dd, //input from other modules
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h_we,t_we,n_we,d_we, //output to table (write enable)
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h_we,t_we,n_we,d_we, //output to table (write enable)
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h_waddr,t_waddr,n_waddr,d_waddr, //output to table (write address)
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h_waddr,t_waddr,n_waddr,d_waddr, //output to table (write address)
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h_wdata,t_wdata,n_wdata,d_wdata, //output to table (write data)
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h_wdata,t_wdata,n_wdata,d_wdata, //output to table (write data)
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HCN,DAC,DMG,CLR,EOC,O //output to other modules
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HCN,DAC,DMG,CLR,EOC,O //output to other modules
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);
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);
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parameter address_bit=9;
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parameter address_bit=9;
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parameter data_bit=38;
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parameter data_bit=38;
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input clk,rst,datavalid,A,B,C,D,fp,fn;
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input clk,rst,datavalid,A,B,C,D,fp,fn;
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input [address_bit-1:0]p,hp,np,tp;
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input [address_bit-1:0]p,hp,np,tp;
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input [data_bit-1:0]dp,dd;
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input [data_bit-1:0]dp,dd;
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output reg h_we,t_we,n_we,d_we;
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output reg h_we,t_we,n_we,d_we;
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output reg[address_bit-1:0]h_waddr,t_waddr,n_waddr,d_waddr;
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output reg[address_bit-1:0]h_waddr,t_waddr,n_waddr,d_waddr;
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output reg[address_bit-1:0]h_wdata,t_wdata,n_wdata;
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output reg[address_bit-1:0]h_wdata,t_wdata,n_wdata;
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output reg[data_bit-1:0]d_wdata;
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output reg[data_bit-1:0]d_wdata;
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output HCN,DAC,DMG,CLR,O;
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output HCN,DAC,DMG,CLR,O;
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output reg EOC;
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output reg EOC;
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reg [address_bit-1:0]cc,h;
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reg [address_bit-1:0]cc,h;
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reg f,HBF;
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reg f,HBF;
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wire Ec,Ep;
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wire Ec,Ep;
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assign DMG=O&~(f&hp==h);
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assign DMG=O&~(f&hp==h);
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assign DAC=D;
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assign DAC=D;
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/////events
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/////events
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assign Ec=(C&~D);
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assign Ec=(C&~D);
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assign Ep=(A&~B);
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assign Ep=(A&~B);
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assign O=(B&D&(~A|~C));
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assign O=(B&D&(~A|~C));
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assign CLR=Ec;
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assign CLR=Ec;
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assign HCN=HBF&(np==p);
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assign HCN=HBF&(np==p);
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////cache cc,h,f
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////cache cc,h,f
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always@(posedge clk or posedge rst)
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always@(posedge clk or posedge rst)
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if(rst)begin
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if(rst)begin
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cc<=0;h<=0;f<=0;
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cc<=0;h<=0;f<=0;
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end
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end
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else if(datavalid)
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else if(datavalid)
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if(Ec)begin
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if(Ec)begin
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cc<=cc+1; //INC
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cc<=cc+1; //INC
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f<=0; //CLR
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f<=0; //CLR
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end
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end
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else if(O)begin
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else if(O)begin
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h<=h_wdata;f<=1; //ET1,ET2,ET3
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h<=h_wdata;f<=1; //ET1,ET2,ET3
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end
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end
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/////table update
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/////table update
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always@*begin
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always@*begin
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h_we=0;h_waddr={address_bit{1'bx}};h_wdata={address_bit{1'bx}};
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h_we=0;h_waddr={address_bit{1'bx}};h_wdata={address_bit{1'bx}};
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t_we=0;t_waddr={address_bit{1'bx}};t_wdata={address_bit{1'bx}};
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t_we=0;t_waddr={address_bit{1'bx}};t_wdata={address_bit{1'bx}};
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n_we=0;n_waddr={address_bit{1'bx}};n_wdata={address_bit{1'bx}};
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n_we=0;n_waddr={address_bit{1'bx}};n_wdata={address_bit{1'bx}};
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d_we=0;d_waddr={address_bit{1'bx}};d_wdata={data_bit{1'bx}};
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d_we=0;d_waddr={address_bit{1'bx}};d_wdata={data_bit{1'bx}};
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EOC=0;HBF=0;
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EOC=0;HBF=0;
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if(Ec)begin
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if(Ec)begin
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n_we=1;n_waddr=cc;n_wdata=cc; //CLR
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n_we=1;n_waddr=cc;n_wdata=cc; //CLR
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h_we=1;h_waddr=cc;h_wdata=cc; //CLR
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h_we=1;h_waddr=cc;h_wdata=cc; //CLR
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case(f)
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case(f)
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0:begin d_we=1;d_waddr=cc;d_wdata=dd;end //DUC
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0:begin d_we=1;d_waddr=cc;d_wdata=dd;end //DUC
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1:begin d_we=1;d_waddr=h;d_wdata=dd;end //DUH
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1:begin d_we=1;d_waddr=h;d_wdata=dd;end //DUH
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endcase
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endcase
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end
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end
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else if(Ep)begin
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else if(Ep)begin
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case(fp)
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case(fp)
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0:begin d_we=1;d_waddr=np;d_wdata=dp; //DBF
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0:begin d_we=1;d_waddr=np;d_wdata=dp; //DBF
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if(fn)EOC=1; end //EOC
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if(fn)EOC=1; end //EOC
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1:begin h_we=1;h_waddr=np;h_wdata=hp;HBF=1;end //HBF
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1:begin h_we=1;h_waddr=np;h_wdata=hp;HBF=1;end //HBF
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endcase
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endcase
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end
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end
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else if(O)
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else if(O)
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case({f,fp})
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case({f,fp})
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2'b00:begin
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2'b00:begin
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h_we=1;h_waddr=np;h_wdata=cc; //ET1
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h_we=1;h_waddr=np;h_wdata=cc; //ET1
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t_we=1;t_waddr=h_wdata;t_wdata=cc;
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t_we=1;t_waddr=h_wdata;t_wdata=cc;
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end
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end
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2'b01:begin
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2'b01:begin
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h_we=1;h_waddr=np;h_wdata=hp; //ET3
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h_we=1;h_waddr=np;h_wdata=hp; //ET3
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t_we=1;t_waddr=h_wdata;t_wdata=cc;
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t_we=1;t_waddr=h_wdata;t_wdata=cc;
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n_we=1;n_waddr=tp;n_wdata=cc; //EM1
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n_we=1;n_waddr=tp;n_wdata=cc; //EM1
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end
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end
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2'b10:begin
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2'b10:begin
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h_we=1;h_waddr=np;h_wdata=h; //ET2
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h_we=1;h_waddr=np;h_wdata=h; //ET2
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t_we=1;t_waddr=h_wdata;t_wdata=cc;
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t_we=1;t_waddr=h_wdata;t_wdata=cc;
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end
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end
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2'b11:begin
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2'b11:begin
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h_we=1;h_waddr=np;h_wdata=hp; //ET3
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h_we=1;h_waddr=np;h_wdata=hp; //ET3
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t_we=1;t_waddr=h_wdata;t_wdata=cc;
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t_we=1;t_waddr=h_wdata;t_wdata=cc;
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n_we=1;n_waddr=tp;n_wdata=h; //EM2
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n_we=1;n_waddr=tp;n_wdata=h; //EM2
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end
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end
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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