-- LOGIC ANALYSER VIEWER
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-- LOGIC ANALYSER VIEWER
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-- this file is only for simulation !!!!!!!!!
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-- this file is only for simulation !!!!!!!!!
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-- this file allows for viewing data obtained by internal logic analyzer
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-- this file allows for viewing data obtained by internal logic analyzer
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-- file la_data.bin should be on your computer
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-- file la_data.bin should be on your computer
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-- this file is obtained by a log_anal.vhd component and others components loaded into a FPGA (virtex)
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-- this file is obtained by a log_anal.vhd component and others components loaded into a FPGA (virtex)
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-- and a proper WISHBONE reads
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-- and a proper WISHBONE reads
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-- readblock la_data.bin adr_start adr_stop
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-- readblock la_data.bin adr_start adr_stop
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-- where adr_start= LA_base_address, adr_stop= LA_base_address + 2^(adr_width-1) + (15)dec
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-- where adr_start= LA_base_address, adr_stop= LA_base_address + 2^(adr_width-1) + (15)dec
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-- the last 16 bytes of la_data.bin contains control registers
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-- the last 16 bytes of la_data.bin contains control registers
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-- adjust data_width and mem_adr_width !!!! to be the same as in the log_anal entity !!!
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-- adjust data_width and mem_adr_width !!!! to be the same as in the log_anal entity !!!
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-- also define your own signals (the same which where connected to log_anal data input
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-- also define your own signals (the same which where connected to log_anal data input
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-- and then assign these signals to proper d(index) data
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-- and then assign these signals to proper d(index) data
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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library IEEE;
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library IEEE;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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entity la_view is
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entity la_view is
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end;
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end;
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architecture la_view_arch of la_view is
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architecture la_view_arch of la_view is
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-- constants - should be the same as generics in the log_anal entity !!!
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-- constants - should be the same as generics in the log_anal entity !!!
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constant data_width: integer:= 16; -- width of the data that are analysed (must be power of 2)
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constant data_width: integer:= 16; -- width of the data that are analysed (must be power of 2)
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constant mem_adr_width: integer:= 9; -- internal memory address width
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constant mem_adr_width: integer:= 9; -- internal memory address width
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-- update the follows values if you want to watch triger
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-- update the follows values if you want to watch triger
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constant trig_width: integer:= 8; -- updatate or no (the circuit can work properly with value 32 also
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constant trig_width: integer:= 8; -- updatate or no (the circuit can work properly with value 32 also
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constant trigger_same_as_data: boolean:= true; -- if the input to the entity log_anal
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constant trigger_same_as_data: boolean:= true; -- if the input to the entity log_anal
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-- data is the same as trig, i.e. trig(trig_width-1 downto 0)= data(trig_width-1 downto 0)
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-- data is the same as trig, i.e. trig(trig_width-1 downto 0)= data(trig_width-1 downto 0)
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------------------------------------ internal LA logic do not change
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------------------------------------ internal LA logic do not change
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constant mem_size: integer:= 2 ** mem_adr_width;
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constant mem_size: integer:= 2 ** mem_adr_width;
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constant file_name: string := "la_data.bin"; -- file name which contains acquired data
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constant file_name: string := "la_data.bin"; -- file name which contains acquired data
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constant file_length: integer:= 2**(mem_adr_width)*data_width/32;
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constant file_length: integer:= 2**(mem_adr_width)*data_width/32;
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-- number of dwords (32-bits) in the file (excluding control registers)
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-- number of dwords (32-bits) in the file (excluding control registers)
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type la_mem_type is array (mem_size-1 downto 0) of std_logic_vector (data_width-1 downto 0);
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type la_mem_type is array (mem_size-1 downto 0) of std_logic_vector (data_width-1 downto 0);
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procedure ReadControlReg(variable stop_count: out integer;
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procedure ReadControlReg(variable stop_count: out integer;
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signal trigger_value: out std_logic_vector(trig_width-1 downto 0) ) is -- read stop counter value form la_data.bin file
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signal trigger_value: out std_logic_vector(trig_width-1 downto 0) ) is -- read stop counter value form la_data.bin file
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variable DataIn: integer;
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variable DataIn: integer;
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variable trig_care: std_logic_vector(trig_width-1 downto 0);
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variable trig_care: std_logic_vector(trig_width-1 downto 0);
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type BIT_VECTOR_FILE is file of integer;
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type BIT_VECTOR_FILE is file of integer;
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file Data_In_File : BIT_VECTOR_FILE;
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file Data_In_File : BIT_VECTOR_FILE;
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begin
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begin
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FILE_OPEN (Data_In_File, file_name, READ_MODE);
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FILE_OPEN (Data_In_File, file_name, READ_MODE);
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for i in 0 to file_length loop
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for i in 0 to file_length loop
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READ (Data_In_File, DataIn );
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READ (Data_In_File, DataIn );
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end loop;
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end loop;
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-- Data_In contains status register (MSBs should be filled with zero
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-- Data_In contains status register (MSBs should be filled with zero
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assert DataIn<256
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assert DataIn<256
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report "Error. Incorrect data format in la_data.bin, check if the same generic values: data_width and mem_adr_width has been set in the log_anal and la_view entities or wrong read size"
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report "Error. Incorrect data format in la_data.bin, check if the same generic values: data_width and mem_adr_width has been set in the log_anal and la_view entities or wrong read size"
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severity failure;
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severity failure;
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assert DataIn<128
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assert DataIn<128
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report "Warning. The log_anal was still in run mode when acquired data were read"
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report "Warning. The log_anal was still in run mode when acquired data were read"
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severity warning;
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severity warning;
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assert DataIn>=64
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assert DataIn>=64
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report "Warning. The log_anal has not finished data acquisition or file format error, check generic values seting and WISHBONE read size"
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report "Warning. The log_anal has not finished data acquisition or file format error, check generic values seting and WISHBONE read size"
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severity warning;
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severity warning;
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READ (Data_In_File, DataIn ); -- stop counter
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READ (Data_In_File, DataIn ); -- stop counter
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assert DataIn< 2**mem_adr_width
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assert DataIn< 2**mem_adr_width
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report "Error. Incorect stop counter value in la_data.bin. Check if the same generic values: data_width and mem_adr_width has been set in the log_anal and la_view entities"
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report "Error. Incorect stop counter value in la_data.bin. Check if the same generic values: data_width and mem_adr_width has been set in the log_anal and la_view entities"
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severity failure;
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severity failure;
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stop_count:= DataIn;
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stop_count:= DataIn;
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READ (Data_In_File, DataIn ); -- trig_value
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READ (Data_In_File, DataIn ); -- trig_value
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trigger_value<= conv_std_logic_vector(DataIn, trig_width);
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trigger_value<= conv_std_logic_vector(DataIn, trig_width);
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READ (Data_In_File, DataIn ); -- trig_care
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READ (Data_In_File, DataIn ); -- trig_care
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trig_care:= conv_std_logic_vector(DataIn, trig_width);
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trig_care:= conv_std_logic_vector(DataIn, trig_width);
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for i in trig_width-1 downto 0 loop
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for i in trig_width-1 downto 0 loop
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if trig_care(i)='0' then
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if trig_care(i)='0' then
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trigger_value(i)<= '-';
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trigger_value(i)<= '-';
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end if;
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end if;
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end loop;
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end loop;
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FILE_CLOSE ( Data_In_File );
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FILE_CLOSE ( Data_In_File );
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end ReadControlReg;
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end ReadControlReg;
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procedure ReadData(variable stop_count: in integer; signal mem : out la_mem_type ) is -- read recorded data from la_data.bin file
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procedure ReadData(variable stop_count: in integer; signal mem : out la_mem_type ) is -- read recorded data from la_data.bin file
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variable DataIn : integer;
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variable DataIn : integer;
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variable Data32 : std_logic_vector(31 downto 0);
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variable Data32 : std_logic_vector(31 downto 0);
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variable address:integer;
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variable address:integer;
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type BIT_VECTOR_FILE is file of integer;
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type BIT_VECTOR_FILE is file of integer;
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file DataInFile : BIT_VECTOR_FILE;
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file DataInFile : BIT_VECTOR_FILE;
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begin
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begin
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address:= (mem_size - stop_count) rem mem_size; -- the start address (rem is for stop_count=0)
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address:= (mem_size - stop_count) rem mem_size; -- the start address (rem is for stop_count=0)
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FILE_OPEN (DataInFile, file_name, READ_MODE);
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FILE_OPEN (DataInFile, file_name, READ_MODE);
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for i in 1 to file_length loop -- for every data in the file
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for i in 1 to file_length loop -- for every data in the file
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READ(DataInFile, DataIn);
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READ(DataInFile, DataIn);
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Data32:= conv_std_logic_vector(DataIn, 32);
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Data32:= conv_std_logic_vector(DataIn, 32);
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for j in 0 to (32/data_width) -1 loop
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for j in 0 to (32/data_width) -1 loop
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mem(address)<= Data32((j+1)*data_width-1 downto j*data_width);
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mem(address)<= Data32((j+1)*data_width-1 downto j*data_width);
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address:= address + 1;
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address:= address + 1;
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if address= mem_size then
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if address= mem_size then
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address:= 0;
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address:= 0;
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end if;
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end if;
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end loop;
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end loop;
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end loop;
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end loop;
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FILE_CLOSE (DataInFile);
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FILE_CLOSE (DataInFile);
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end;
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end;
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signal la_mem : la_mem_type; -- data read form la_data.bin file
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signal la_mem : la_mem_type; -- data read form la_data.bin file
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signal d: std_logic_vector(data_width-1 downto 0); -- data recorder by the LA
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signal d: std_logic_vector(data_width-1 downto 0); -- data recorder by the LA
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signal trigger_value: std_logic_vector(trig_width-1 downto 0); -- the value specified by writes to the trigger value and care registers
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signal trigger_value: std_logic_vector(trig_width-1 downto 0); -- the value specified by writes to the trigger value and care registers
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signal trigger: std_logic; -- trigger condition is now satisfied
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signal trigger: std_logic; -- trigger condition is now satisfied
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signal clk: std_logic; -- data has been recoreded according to this clock activity
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signal clk: std_logic; -- data has been recoreded according to this clock activity
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-----------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- User area (changes can be done here)
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-- User area (changes can be done here)
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-- define here your signal names
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-- define here your signal names
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signal counter: std_logic_vector(data_width-1 downto 0);
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signal counter: std_logic_vector(data_width-1 downto 0);
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begin
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begin
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-- write here which signal is assigned to which LA data bus (see log_anal instantiation)
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-- write here which signal is assigned to which LA data bus (see log_anal instantiation)
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-- signal 'd' is the same as data input in the log_anal entity
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-- signal 'd' is the same as data input in the log_anal entity
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counter<= d;
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counter<= d;
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-- clk generation
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-- clk generation
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process begin
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process begin
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wait for 10 ns; -- this value can be change freely
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wait for 10 ns; -- this value can be change freely
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clk<= '0';
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clk<= '0';
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wait for 10 ns;
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wait for 10 ns;
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clk<= '1';
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clk<= '1';
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end process;
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end process;
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-------------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------------
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-- Internal LA logic do not change it !!!
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-- Internal LA logic do not change it !!!
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process
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process
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variable Initialize : integer := 0; -- initialisation flag
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variable Initialize : integer := 0; -- initialisation flag
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variable stop_count : integer; -- the count points where the last data has been written to the LA memory
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variable stop_count : integer; -- the count points where the last data has been written to the LA memory
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begin
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begin
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if Initialize=0 then -- run only one time at the beginning
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if Initialize=0 then -- run only one time at the beginning
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ReadControlReg(stop_count, trigger_value);
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ReadControlReg(stop_count, trigger_value);
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ReadData(stop_count, la_mem); -- read data recorded by the LA
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ReadData(stop_count, la_mem); -- read data recorded by the LA
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Initialize := 1;
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Initialize := 1;
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wait for 1000 ms;
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wait for 1000 ms;
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end if;
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end if;
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end process;
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end process;
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process(clk)
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process(clk)
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variable i: integer:= 0;
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variable i: integer:= 0;
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variable trigger_tmp: std_logic;
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variable trigger_tmp: std_logic;
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variable d_tmp: std_logic_vector(data_width-1 downto 0);
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variable d_tmp: std_logic_vector(data_width-1 downto 0);
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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d_tmp:= la_mem(i); -- data recorded in the LA
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d_tmp:= la_mem(i); -- data recorded in the LA
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d<= d_tmp;
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d<= d_tmp;
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-- trigger logic
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-- trigger logic
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if trigger_same_as_data=true and trig_width <= data_width then
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if trigger_same_as_data=true and trig_width <= data_width then
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trigger_tmp:= '1';
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trigger_tmp:= '1';
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for j in trig_width-1 downto 0 loop
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for j in trig_width-1 downto 0 loop
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if trigger_value(j)/= '-' then -- check only if not don't care
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if trigger_value(j)/= '-' then -- check only if not don't care
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trigger_tmp:= trigger_tmp AND not (trigger_value(j) XOR d_tmp(j));
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trigger_tmp:= trigger_tmp AND not (trigger_value(j) XOR d_tmp(j));
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end if;
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end if;
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end loop;
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end loop;
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trigger<= trigger_tmp;
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trigger<= trigger_tmp;
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else -- do not show trigger because trigger data are different from watched data
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else -- do not show trigger because trigger data are different from watched data
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trigger<= 'Z';
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trigger<= 'Z';
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end if;
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end if;
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i:= i +1;
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i:= i +1;
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if i= mem_size then
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if i= mem_size then
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i:= mem_size-1;
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i:= mem_size-1;
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assert false
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assert false
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report "O.K. All acquired data in the LA has already been shown"
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report "O.K. All acquired data in the LA has already been shown"
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severity failure;
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severity failure;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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assert data_width=32 or data_width=16 or data_width=8
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assert data_width=32 or data_width=16 or data_width=8
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report "Error in la_view: constant data_width must be 8, 16 or 32"
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report "Error in la_view: constant data_width must be 8, 16 or 32"
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severity failure;
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severity failure;
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end la_view_arch;
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end la_view_arch;
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-- logic analyser (LA) for FPGAs
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-- logic analyser (LA) for FPGAs
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-- ver 1.0
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-- ver 1.0
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-- Author: Ernest Jamro
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-- Author: Ernest Jamro
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--//////////////////////////////////////////////////////////////////////
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--//////////////////////////////////////////////////////////////////////
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--//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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--//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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--//// ////
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--//// ////
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--//// This source file may be used and distributed without ////
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--//// This source file may be used and distributed without ////
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--/// restriction provided that this copyright statement is not ////
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--/// restriction provided that this copyright statement is not ////
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--//// removed from the file and that any derivative work contains ////
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--//// removed from the file and that any derivative work contains ////
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--//// the original copyright notice and the associated disclaimer. ////
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--//// the original copyright notice and the associated disclaimer. ////
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--//// ////
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--//// ////
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--//// This source file is free software; you can redistribute it ////
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--//// This source file is free software; you can redistribute it ////
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--//// and/or modify it under the terms of the GNU Lesser General ////
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--//// and/or modify it under the terms of the GNU Lesser General ////
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--//// Public License as published by the Free Software Foundation; ////
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--//// Public License as published by the Free Software Foundation; ////
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--//// either version 2.1 of the License, or (at your option) any ////
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--//// either version 2.1 of the License, or (at your option) any ////
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--//// later version. ////
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--//// later version. ////
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--//// ////
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--//// ////
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--//// This source is distributed in the hope that it will be ////
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--//// This source is distributed in the hope that it will be ////
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--//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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--//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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--//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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--//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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--//// PURPOSE. See the GNU Lesser General Public License for more ////
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--//// PURPOSE. See the GNU Lesser General Public License for more ////
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--//// details. ////
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--//// details. ////
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--//// ////
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--//// ////
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--//// You should have received a copy of the GNU Lesser General ////
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--//// You should have received a copy of the GNU Lesser General ////
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--//// Public License along with this source; if not, download it ////
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--//// Public License along with this source; if not, download it ////
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--//// from <http://www.opencores.org/lgpl.shtml> ////
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--//// from <http://www.opencores.org/lgpl.shtml> ////
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