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Welcome to LogicProbe!
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Welcome to LogicProbe!
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1) What is it?
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1) What is it?
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LogicProbe is a very simple logic analyzer which can be run on
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LogicProbe is a very simple logic analyzer which can be run on
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an FPGA in parallel with the "device under test". The analyzer
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an FPGA in parallel with the "device under test". The analyzer
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has a width of 128 data channels, and is 512 samples deep. It
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has a width of 128 data channels, and is 512 samples deep. It
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has a trigger (i.e., it starts catching the channels when this
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has a trigger (i.e., it starts catching the channels when this
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signal got active once), and a sample enable (i.e., it does only
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signal got active once), and a sample enable (i.e., it does only
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sample the channels when this line is 1). It uses the block RAM
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sample the channels when this line is 1). It uses the block RAM
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on the FPGA to store the samples in real-time. When the sample
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on the FPGA to store the samples in real-time. When the sample
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buffer is full, it begins to transmit the samples through a UART
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buffer is full, it begins to transmit the samples through a UART
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(also included in the code) over the serial line to a PC where
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(also included in the code) over the serial line to a PC where
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the sample values are stored in a file. A simple listing program
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the sample values are stored in a file. A simple listing program
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allows to view the samples as hexadecimal values.
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allows to view the samples as hexadecimal values.
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2) How do I use it?
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2) How do I use it?
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You simply have to instanciate the module described below and setup
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You simply have to instanciate the module described below and setup
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the constraints file so that "serial_out" is connected to the transmit
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the constraints file so that "serial_out" is connected to the transmit
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data line of an RS232 connector (via appropriate level shifters, of
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data line of an RS232 connector (via appropriate level shifters, of
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course). The line speed is fixed at 38400 bps; this should certainly
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course). The line speed is fixed at 38400 bps; this should certainly
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be made a parameter of the design in the next version. Connect a PC
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be made a parameter of the design in the next version. Connect a PC
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to the other end of the serial line and run the "receive" program,
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to the other end of the serial line and run the "receive" program,
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which stores the transmitted samples into a file. You can then use
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which stores the transmitted samples into a file. You can then use
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the "display" program to examine the samples as hexadecimal numbers.
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the "display" program to examine the samples as hexadecimal numbers.
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Here is the interface to the analyzer module:
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Here is the interface to the analyzer module:
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module LogicProbe(clock, reset, trigger, sample, channels, serial_out);
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module LogicProbe(clock, reset, trigger, sample, channels, serial_out);
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input clock; // master clock, also used for sampling
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input clock; // master clock, also used for sampling
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input reset; // master reset
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input reset; // master reset
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input trigger; // start sampling when this line is 1
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input trigger; // start sampling when this line is 1
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input sample; // enable sampling when this line is 1
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input sample; // enable sampling when this line is 1
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input [127:0] channels; // the data to be sampled
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input [127:0] channels; // the data to be sampled
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output serial_out; // serial line to the PC
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output serial_out; // serial line to the PC
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3) What do the directories and files in this package contain?
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3) What do the directories and files in this package contain?
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README this file
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README this file
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COPYING BSD license
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COPYING BSD license
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Makefile Makefile for building the project
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Makefile Makefile for building the project
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src source files
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src source files
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Makefile controls the build process on this level
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Makefile controls the build process on this level
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fpga synthesizable Verilog (for running on the FPGA)
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fpga synthesizable Verilog (for running on the FPGA)
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LogicProbe.v the logic analyzer proper
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LogicProbe.v the logic analyzer proper
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pc C source files (for running on the PC)
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pc C source files (for running on the PC)
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Makefile for building the analyzer programs
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Makefile for building the analyzer programs
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receive.c RS232 receiver program
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receive.c RS232 receiver program
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display.c sample value viewer
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display.c sample value viewer
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tst test case, simulated as well as running on FPGAs
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tst test case, simulated as well as running on FPGAs
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Makefile controls the build process on this level
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Makefile controls the build process on this level
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sim-c simulation program in C
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sim-c simulation program in C
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Makefile runs the simulation, generates reference data
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Makefile runs the simulation, generates reference data
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lfsr128.c 128 bit LFSR
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lfsr128.c 128 bit LFSR
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sim-v Verilog source to be simulated with Icarus Verilog
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sim-v Verilog source to be simulated with Icarus Verilog
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Makefile controls the simulation
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Makefile controls the simulation
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top.v top-level simulation environment
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top.v top-level simulation environment
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top.cfg config file for GTK wave viewer
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top.cfg config file for GTK wave viewer
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lfsr128.v same LFSR as in C, but now in Verilog
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lfsr128.v same LFSR as in C, but now in Verilog
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boards same LFSR as in sim-v, with LogicProbe attached,
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boards same LFSR as in sim-v, with LogicProbe attached,
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configured for different FPGA evaluation boards
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configured for different FPGA evaluation boards
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4) What else do I need?
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4) What else do I need?
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If you want to run the tests, you need a Verilog simulator (I used
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If you want to run the tests, you need a Verilog simulator (I used
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Icarus Verilog) and a VCD wave viewer (I used GTK-Wave). If you want
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Icarus Verilog) and a VCD wave viewer (I used GTK-Wave). If you want
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to use the analyzer in an FPGA, you must synthesize it (I used Xilinx
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to use the analyzer in an FPGA, you must synthesize it (I used Xilinx
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ISE 14.5). And you need a C compiler, preferably on a Linux system,
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ISE 14.5). And you need a C compiler, preferably on a Linux system,
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to receive and display the sample values.
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to receive and display the sample values.
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5) Has the analyzer been used outside the test case?
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5) Has the analyzer been used outside the test case?
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Yes, it was instrumental in finding an error in my 32-bit CPU
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Yes, it was instrumental in finding an error in my 32-bit CPU
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which prohibited even the first instruction fetch from memory.
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which prohibited even the first instruction fetch from memory.
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Simulation was of no help; the error didn't show up there. As
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Simulation was of no help; the error didn't show up there. As
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it turned out, I used initialization statements, which of course
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it turned out, I used initialization statements, which of course
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couldn't be synthesized - so the start conditions inside the FPGA
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couldn't be synthesized - so the start conditions inside the FPGA
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differed from those of the simulation.
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differed from those of the simulation.
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If you have any questions, write to
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If you have any questions, write to
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Hellwig.Geisse@mni.thm.de
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Hellwig.Geisse@mni.thm.de
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Enjoy!
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Enjoy!
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Hellwig
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Hellwig
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