//
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//
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// lfsr128.v -- a linear feedback shift register with 128 bits
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// lfsr128.v -- a linear feedback shift register with 128 bits
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// (actually constructed from 4 instances of a 32-bit lfsr)
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// (actually constructed from 4 instances of a 32-bit lfsr)
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//
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//
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`include "../../src/fpga/LogicProbe.v"
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`include "../../src/fpga/LogicProbe.v"
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module lfsr128(clk, reset_in_n, s, rs232_txd);
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module lfsr128(clk, reset_in_n, s, rs232_txd);
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input clk;
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input clk;
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input reset_in_n;
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input reset_in_n;
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output [3:0] s;
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output [3:0] s;
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output rs232_txd;
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output rs232_txd;
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wire reset;
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wire reset;
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reg [3:0] reset_counter;
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reg [3:0] reset_counter;
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reg [31:0] lfsr0;
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reg [31:0] lfsr0;
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reg [31:0] lfsr1;
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reg [31:0] lfsr1;
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reg [31:0] lfsr2;
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reg [31:0] lfsr2;
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reg [31:0] lfsr3;
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reg [31:0] lfsr3;
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wire trigger;
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wire trigger;
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wire sample;
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wire sample;
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wire [127:0] log_data;
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wire [127:0] log_data;
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assign reset = (reset_counter == 4'hF) ? 0 : 1;
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assign reset = (reset_counter == 4'hF) ? 0 : 1;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset_in_n == 0) begin
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if (reset_in_n == 0) begin
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reset_counter <= 4'h0;
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reset_counter <= 4'h0;
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end else begin
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end else begin
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if (reset_counter != 4'hF) begin
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if (reset_counter != 4'hF) begin
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reset_counter <= reset_counter + 1;
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reset_counter <= reset_counter + 1;
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end
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end
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end
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end
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset == 1) begin
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if (reset == 1) begin
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lfsr0 <= 32'hC70337DB;
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lfsr0 <= 32'hC70337DB;
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lfsr1 <= 32'h7F4D514F;
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lfsr1 <= 32'h7F4D514F;
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lfsr2 <= 32'h75377599;
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lfsr2 <= 32'h75377599;
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lfsr3 <= 32'h7D5937A3;
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lfsr3 <= 32'h7D5937A3;
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end else begin
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end else begin
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if (lfsr0[0] == 0) begin
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if (lfsr0[0] == 0) begin
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lfsr0 <= lfsr0 >> 1;
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lfsr0 <= lfsr0 >> 1;
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end else begin
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end else begin
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lfsr0 <= (lfsr0 >> 1) ^ 32'hD0000001;
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lfsr0 <= (lfsr0 >> 1) ^ 32'hD0000001;
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end
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end
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if (lfsr1[0] == 0) begin
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if (lfsr1[0] == 0) begin
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lfsr1 <= lfsr1 >> 1;
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lfsr1 <= lfsr1 >> 1;
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end else begin
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end else begin
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lfsr1 <= (lfsr1 >> 1) ^ 32'hD0000001;
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lfsr1 <= (lfsr1 >> 1) ^ 32'hD0000001;
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end
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end
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if (lfsr2[0] == 0) begin
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if (lfsr2[0] == 0) begin
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lfsr2 <= lfsr2 >> 1;
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lfsr2 <= lfsr2 >> 1;
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end else begin
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end else begin
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lfsr2 <= (lfsr2 >> 1) ^ 32'hD0000001;
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lfsr2 <= (lfsr2 >> 1) ^ 32'hD0000001;
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end
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end
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if (lfsr3[0] == 0) begin
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if (lfsr3[0] == 0) begin
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lfsr3 <= lfsr3 >> 1;
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lfsr3 <= lfsr3 >> 1;
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end else begin
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end else begin
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lfsr3 <= (lfsr3 >> 1) ^ 32'hD0000001;
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lfsr3 <= (lfsr3 >> 1) ^ 32'hD0000001;
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end
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end
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end
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end
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end
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end
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assign s[3] = lfsr0[27];
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assign s[3] = lfsr0[27];
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assign s[2] = lfsr1[13];
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assign s[2] = lfsr1[13];
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assign s[1] = lfsr2[23];
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assign s[1] = lfsr2[23];
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assign s[0] = lfsr3[11];
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assign s[0] = lfsr3[11];
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assign trigger = (lfsr0 == 32'h7119C0CD) ? 1 : 0;
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assign trigger = (lfsr0 == 32'h7119C0CD) ? 1 : 0;
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assign sample = 1;
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assign sample = 1;
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assign log_data = { lfsr0, lfsr1, lfsr2, lfsr3 };
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assign log_data = { lfsr0, lfsr1, lfsr2, lfsr3 };
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LogicProbe lp(clk, reset, trigger, sample, log_data, rs232_txd);
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LogicProbe lp(clk, reset, trigger, sample, log_data, rs232_txd);
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endmodule
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endmodule
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