URL
https://opencores.org/ocsvn/logicprobe/logicprobe/trunk
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Rev 12 |
Rev 19 |
This board is equipped with a single RS-232 connector. The lines
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This board is equipped with a single RS-232 connector. The lines
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TXD, RXD, RTS, and CTS are connected (via level shifters) to the
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TXD, RXD, RTS, and CTS are connected (via level shifters) to the
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FPGA. Because in another project, two serial lines were required
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FPGA. Because in another project, two serial lines were required
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(and no hardware flow control was necessary), the signals RTS and
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(and no hardware flow control was necessary), the signals RTS and
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CTS were used as TXD and RXD, respectively, in a separate (third)
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CTS were used as TXD and RXD, respectively, in a separate (third)
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connector. In this way the single serial line with flow control
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connector. In this way the single serial line with flow control
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has been split into two serial lines without flow control. The
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has been split into two serial lines without flow control. The
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constraints file given here uses the second TXD line as output
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constraints file given here uses the second TXD line as output
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for the logic analyzer. This can be changed to the original TXD
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for the logic analyzer. This can be changed to the original TXD
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line by specifying "j2" instead of "f4" in the constraints file.
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line by specifying "j2" instead of "f4" in the constraints file.
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