OpenCores
URL https://opencores.org/ocsvn/logicprobe/logicprobe/trunk

Subversion Repositories logicprobe

[/] [logicprobe/] [tags/] [LogicProbe-1.1/] [tst/] [sim-v/] [Makefile] - Diff between revs 5 and 19

Only display areas with differences | Details | Blame | View Log

Rev 5 Rev 19
#
#
# Makefile to build a simulation of the test circuit
# Makefile to build a simulation of the test circuit
#
#
all:            dump.vcd
all:            dump.vcd
show:           dump.vcd
show:           dump.vcd
                gtkwave dump.vcd top.cfg
                gtkwave dump.vcd top.cfg
dump.vcd:       top
dump.vcd:       top
                ./top
                ./top
top:            top.v
top:            top.v
                iverilog -Wall -o top top.v
                iverilog -Wall -o top top.v
clean:
clean:
                rm -f *~ top dump.vcd
                rm -f *~ top dump.vcd
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.