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https://opencores.org/ocsvn/lpffir/lpffir/trunk
[/] [lpffir/] [trunk/] [doc/] [src/] [axis_timing.tim] - Diff between revs 6 and 8
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Rev 6 |
Rev 8 |
Timing Analyzer Settings
|
Timing Analyzer Settings
|
Version: 0.991
|
Version: 0.991
|
Time_Scale: 1.0E-9
|
Time_Scale: 1.0E-9
|
Time_Per_Division: 64
|
Time_Per_Division: 64
|
Number_Divisions: 160
|
Number_Divisions: 160
|
Start_Time: 0
|
Start_Time: 0
|
End_Time: 750
|
End_Time: 750
|
Part_Constraint
|
Part_Constraint
|
Name: thold
|
Name: thold
|
Min_Constraint: 4.0
|
Min_Constraint: 4.0
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Max_Constraint: 4.0
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Max_Constraint: 4.0
|
Description: Example hold constraint
|
Description: Example hold constraint
|
Part_Constraint_End
|
Part_Constraint_End
|
Part_Constraint
|
Part_Constraint
|
Name: tsetup
|
Name: tsetup
|
Min_Constraint: 10.0
|
Min_Constraint: 10.0
|
Max_Constraint: 10.0
|
Max_Constraint: 10.0
|
Description: Example setup constraint
|
Description: Example setup constraint
|
Part_Constraint_End
|
Part_Constraint_End
|
Jitter_Margin
|
Jitter_Margin
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Name: p1jitter
|
Name: p1jitter
|
Plus_Margin: 1.0
|
Plus_Margin: 1.0
|
Minus_Margin: 1.0
|
Minus_Margin: 1.0
|
Description: Example part jitter
|
Description: Example part jitter
|
Jitter_Margin_End
|
Jitter_Margin_End
|
Jitter_Margin
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Jitter_Margin
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Name: p2jitter
|
Name: p2jitter
|
Plus_Margin: 0.5
|
Plus_Margin: 0.5
|
Minus_Margin: 0.5
|
Minus_Margin: 0.5
|
Description: Example part jitter
|
Description: Example part jitter
|
Jitter_Margin_End
|
Jitter_Margin_End
|
Digital_Clock
|
Digital_Clock
|
Position: 1
|
Position: 1
|
Name: aclk_i
|
Name: aclk_i
|
Frequency: 1.0E7
|
Frequency: 1.0E7
|
Duty_Cycle: 50
|
Duty_Cycle: 50
|
Start_Delay: 0.0
|
Start_Delay: 0.0
|
Start_State: L
|
Start_State: L
|
Rise_Time: 5.0
|
Rise_Time: 5.0
|
Fall_Time: 5.0
|
Fall_Time: 5.0
|
IO_Type: Input
|
IO_Type: Input
|
Digital_Clock_End
|
Digital_Clock_End
|
Digital_Signal
|
Digital_Signal
|
Position: 2
|
Position: 2
|
Name: rx_tlast_i
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Name: rx_tlast_i
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Start_State: L
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Start_State: L
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Rise_Time: 5.0
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Rise_Time: 5.0
|
Fall_Time: 5.0
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Fall_Time: 5.0
|
IO_Type: Input
|
IO_Type: Input
|
Sync_Clock: aclk_i
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Sync_Clock: aclk_i
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Edge
|
Edge
|
Min: 556.211
|
Min: 556.211
|
Max: 556.211
|
Max: 556.211
|
State: H
|
State: H
|
Edge_End
|
Edge_End
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Edge
|
Edge
|
Min: 656.211
|
Min: 656.211
|
Max: 656.211
|
Max: 656.211
|
State: L
|
State: L
|
Edge_End
|
Edge_End
|
Digital_Signal_End
|
Digital_Signal_End
|
Digital_Signal
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Digital_Signal
|
Position: 3
|
Position: 3
|
Name: rx_tvalid_i
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Name: rx_tvalid_i
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Start_State: L
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Start_State: L
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Rise_Time: 5.0
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Rise_Time: 5.0
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Fall_Time: 5.0
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Fall_Time: 5.0
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IO_Type: Input
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IO_Type: Input
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Sync_Clock: aclk_i
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Sync_Clock: aclk_i
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Edge
|
Edge
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Min: 53.311
|
Min: 53.311
|
Max: 172.471
|
Max: 172.471
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State: H
|
State: H
|
Edge_End
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Edge_End
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Edge
|
Edge
|
Min: 453.981
|
Min: 453.981
|
Max: 453.981
|
Max: 453.981
|
State: L
|
State: L
|
Edge_End
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Edge_End
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Edge
|
Edge
|
Min: 557.201
|
Min: 557.201
|
Max: 557.201
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Max: 557.201
|
State: H
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State: H
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Edge_End
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Edge_End
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Edge
|
Edge
|
Min: 657.201
|
Min: 657.201
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Max: 657.201
|
Max: 657.201
|
State: L
|
State: L
|
Edge_End
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Edge_End
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Digital_Signal_End
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Digital_Signal_End
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Digital_Signal
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Digital_Signal
|
Position: 4
|
Position: 4
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Name: rx_tready_o
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Name: rx_tready_o
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Start_State: L
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Start_State: L
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Rise_Time: 5.0
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Rise_Time: 5.0
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Fall_Time: 5.0
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Fall_Time: 5.0
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IO_Type: Output
|
IO_Type: Output
|
Sync_Clock: aclk_i
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Sync_Clock: aclk_i
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Edge
|
Edge
|
Min: 98.781
|
Min: 98.781
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Max: 98.781
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Max: 98.781
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State: H
|
State: H
|
Edge_End
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Edge_End
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Edge
|
Edge
|
Min: 157.201
|
Min: 157.201
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Max: 157.201
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Max: 157.201
|
State: L
|
State: L
|
Edge_End
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Edge_End
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Edge
|
Edge
|
Min: 257.201
|
Min: 257.201
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Max: 257.201
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Max: 257.201
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State: H
|
State: H
|
Edge_End
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Edge_End
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Edge
|
Edge
|
Min: 868.401
|
Min: 868.401
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Max: 868.401
|
Max: 868.401
|
State: L
|
State: L
|
Edge_End
|
Edge_End
|
Digital_Signal_End
|
Digital_Signal_End
|
Digital_Bus
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Digital_Bus
|
Position: 5
|
Position: 5
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Name: rx_tdate_i[7:0]
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Name: rx_tdata_i[15:0]
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Start_State: X
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Start_State: X
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State_Format: Text
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State_Format: Text
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Rise_Time: 5.0
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Rise_Time: 5.0
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Fall_Time: 5.0
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Fall_Time: 5.0
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IO_Type: Input
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IO_Type: Input
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Sync_Clock: aclk_i
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Sync_Clock: aclk_i
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Edge
|
Edge
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Min: 53.151
|
Min: 53.151
|
Max: 53.151
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Max: 53.151
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State: DI1
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State: DI1
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Edge_End
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Edge_End
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Edge
|
Edge
|
Min: 156.031
|
Min: 156.031
|
Max: 156.031
|
Max: 156.031
|
State: DI2
|
State: DI2
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Edge_End
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Edge_End
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Edge
|
Edge
|
Min: 357.731
|
Min: 357.731
|
Max: 357.731
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Max: 357.731
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State: DI3
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State: DI3
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Edge_End
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Edge_End
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Edge
|
Edge
|
Min: 453.121
|
Min: 453.121
|
Max: 453.121
|
Max: 453.121
|
State: X
|
State: X
|
Edge_End
|
Edge_End
|
Edge
|
Edge
|
Min: 557.731
|
Min: 557.731
|
Max: 557.731
|
Max: 557.731
|
State: DI4
|
State: DI4
|
Edge_End
|
Edge_End
|
Edge
|
Edge
|
Min: 657.731
|
Min: 657.731
|
Max: 657.731
|
Max: 657.731
|
State: X
|
State: X
|
Edge_End
|
Edge_End
|
Edge
|
Edge
|
Min: 880.091
|
Min: 880.091
|
Max: 880.091
|
Max: 880.091
|
State: Z
|
State: Z
|
Edge_End
|
Edge_End
|
Digital_Bus_End
|
Digital_Bus_End
|
Digital_Signal
|
Digital_Signal
|
Position: 6
|
Position: 6
|
Name: tx_tlast_o
|
Name: tx_tlast_o
|
Start_State: L
|
Start_State: L
|
Rise_Time: 5.0
|
Rise_Time: 5.0
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Fall_Time: 5.0
|
Fall_Time: 5.0
|
IO_Type: Output
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IO_Type: Output
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Edge
|
Edge
|
Min: 556.211
|
Min: 556.211
|
Max: 556.211
|
Max: 556.211
|
State: H
|
State: H
|
Edge_End
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Edge_End
|
Edge
|
Edge
|
Min: 656.211
|
Min: 656.211
|
Max: 656.211
|
Max: 656.211
|
State: L
|
State: L
|
Edge_End
|
Edge_End
|
Digital_Signal_End
|
Digital_Signal_End
|
Digital_Signal
|
Digital_Signal
|
Position: 7
|
Position: 7
|
Name: tx_tvalid_o
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Name: tx_tvalid_o
|
Start_State: L
|
Start_State: L
|
Rise_Time: 5.0
|
Rise_Time: 5.0
|
Fall_Time: 5.0
|
Fall_Time: 5.0
|
IO_Type: Output
|
IO_Type: Output
|
Edge
|
Edge
|
Min: 53.311
|
Min: 53.311
|
Max: 53.311
|
Max: 53.311
|
State: H
|
State: H
|
Edge_End
|
Edge_End
|
Edge
|
Edge
|
Min: 453.981
|
Min: 453.981
|
Max: 453.981
|
Max: 453.981
|
State: L
|
State: L
|
Edge_End
|
Edge_End
|
Edge
|
Edge
|
Min: 557.201
|
Min: 557.201
|
Max: 557.201
|
Max: 557.201
|
State: H
|
State: H
|
Edge_End
|
Edge_End
|
Edge
|
Edge
|
Min: 657.201
|
Min: 657.201
|
Max: 657.201
|
Max: 657.201
|
State: L
|
State: L
|
Edge_End
|
Edge_End
|
Digital_Signal_End
|
Digital_Signal_End
|
Digital_Signal
|
Digital_Signal
|
Position: 8
|
Position: 8
|
Name: tx_tready_i
|
Name: tx_tready_i
|
Start_State: L
|
Start_State: L
|
Rise_Time: 5.0
|
Rise_Time: 5.0
|
Fall_Time: 5.0
|
Fall_Time: 5.0
|
IO_Type: Input
|
IO_Type: Input
|
Edge
|
Edge
|
Min: 98.781
|
Min: 98.781
|
Max: 98.781
|
Max: 98.781
|
State: H
|
State: H
|
Edge_End
|
Edge_End
|
Edge
|
Edge
|
Min: 157.201
|
Min: 157.201
|
Max: 157.201
|
Max: 157.201
|
State: L
|
State: L
|
Edge_End
|
Edge_End
|
Edge
|
Edge
|
Min: 257.201
|
Min: 257.201
|
Max: 257.201
|
Max: 257.201
|
State: H
|
State: H
|
Edge_End
|
Edge_End
|
Edge
|
Edge
|
Min: 868.401
|
Min: 868.401
|
Max: 868.401
|
Max: 868.401
|
State: L
|
State: L
|
Edge_End
|
Edge_End
|
Digital_Signal_End
|
Digital_Signal_End
|
Digital_Bus
|
Digital_Bus
|
Position: 9
|
Position: 9
|
Name: tx_tdate_o[7:0]
|
Name: tx_tdata_o[15:0]
|
Start_State: X
|
Start_State: X
|
State_Format: Text
|
State_Format: Text
|
Rise_Time: 5.0
|
Rise_Time: 5.0
|
Fall_Time: 5.0
|
Fall_Time: 5.0
|
IO_Type: Output
|
IO_Type: Output
|
Edge
|
Edge
|
Min: 53.151
|
Min: 53.151
|
Max: 53.151
|
Max: 53.151
|
State: DO1
|
State: DO1
|
Edge_End
|
Edge_End
|
Edge
|
Edge
|
Min: 156.031
|
Min: 156.031
|
Max: 156.031
|
Max: 156.031
|
State: DO2
|
State: DO2
|
Edge_End
|
Edge_End
|
Edge
|
Edge
|
Min: 357.731
|
Min: 357.731
|
Max: 357.731
|
Max: 357.731
|
State: DO3
|
State: DO3
|
Edge_End
|
Edge_End
|
Edge
|
Edge
|
Min: 453.121
|
Min: 453.121
|
Max: 453.121
|
Max: 453.121
|
State: X
|
State: X
|
Edge_End
|
Edge_End
|
Edge
|
Edge
|
Min: 557.731
|
Min: 557.731
|
Max: 557.731
|
Max: 557.731
|
State: DO4
|
State: DO4
|
Edge_End
|
Edge_End
|
Edge
|
Edge
|
Min: 657.731
|
Min: 657.731
|
Max: 657.731
|
Max: 657.731
|
State: X
|
State: X
|
Edge_End
|
Edge_End
|
Edge
|
Edge
|
Min: 880.091
|
Min: 880.091
|
Max: 880.091
|
Max: 880.091
|
State: Z
|
State: Z
|
Edge_End
|
Edge_End
|
Digital_Bus_End
|
Digital_Bus_End
|
StateBar
|
StateBar
|
State_Name: C2
|
State_Name: C2
|
Line_Type: Dashed
|
Line_Type: Dashed
|
Edge_Position: 50
|
Edge_Position: 50
|
State_Color: #000000
|
State_Color: #000000
|
Font_Name: Dialog
|
Font_Name: Dialog
|
Font_Style: 0
|
Font_Style: 0
|
Font_Size: 12
|
Font_Size: 12
|
Signal_Type: DigitalClock
|
Signal_Type: DigitalClock
|
Signal_Name: aclk_i
|
Signal_Name: aclk_i
|
Edge_At: 5
|
Edge_At: 5
|
OffsetX: 0
|
OffsetX: 0
|
OffsetY: 0
|
OffsetY: 0
|
StateBar_End
|
StateBar_End
|
StateBar
|
StateBar
|
State_Name: C3
|
State_Name: C3
|
Line_Type: Dashed
|
Line_Type: Dashed
|
Edge_Position: 50
|
Edge_Position: 50
|
State_Color: #000000
|
State_Color: #000000
|
Font_Name: Dialog
|
Font_Name: Dialog
|
Font_Style: 0
|
Font_Style: 0
|
Font_Size: 12
|
Font_Size: 12
|
Signal_Type: DigitalClock
|
Signal_Type: DigitalClock
|
Signal_Name: aclk_i
|
Signal_Name: aclk_i
|
Edge_At: 7
|
Edge_At: 7
|
OffsetX: 0
|
OffsetX: 0
|
OffsetY: 0
|
OffsetY: 0
|
StateBar_End
|
StateBar_End
|
StateBar
|
StateBar
|
State_Name: C1
|
State_Name: C1
|
Line_Type: Dashed
|
Line_Type: Dashed
|
Edge_Position: 50
|
Edge_Position: 50
|
State_Color: #000000
|
State_Color: #000000
|
Font_Name: Dialog
|
Font_Name: Dialog
|
Font_Style: 0
|
Font_Style: 0
|
Font_Size: 12
|
Font_Size: 12
|
Signal_Type: DigitalClock
|
Signal_Type: DigitalClock
|
Signal_Name: aclk_i
|
Signal_Name: aclk_i
|
Edge_At: 3
|
Edge_At: 3
|
OffsetX: 0
|
OffsetX: 0
|
OffsetY: 0
|
OffsetY: 0
|
StateBar_End
|
StateBar_End
|
StateBar
|
StateBar
|
State_Name: C4
|
State_Name: C4
|
Line_Type: Dashed
|
Line_Type: Dashed
|
Edge_Position: 50
|
Edge_Position: 50
|
State_Color: #000000
|
State_Color: #000000
|
Font_Name: Dialog
|
Font_Name: Dialog
|
Font_Style: 0
|
Font_Style: 0
|
Font_Size: 12
|
Font_Size: 12
|
Signal_Type: DigitalClock
|
Signal_Type: DigitalClock
|
Signal_Name: aclk_i
|
Signal_Name: aclk_i
|
Edge_At: 9
|
Edge_At: 9
|
OffsetX: 0
|
OffsetX: 0
|
OffsetY: 0
|
OffsetY: 0
|
StateBar_End
|
StateBar_End
|
StateBar
|
StateBar
|
State_Name: C5
|
State_Name: C5
|
Line_Type: Dashed
|
Line_Type: Dashed
|
Edge_Position: 50
|
Edge_Position: 50
|
State_Color: #000000
|
State_Color: #000000
|
Font_Name: Dialog
|
Font_Name: Dialog
|
Font_Style: 0
|
Font_Style: 0
|
Font_Size: 12
|
Font_Size: 12
|
Signal_Type: DigitalClock
|
Signal_Type: DigitalClock
|
Signal_Name: aclk_i
|
Signal_Name: aclk_i
|
Edge_At: 11
|
Edge_At: 11
|
OffsetX: 0
|
OffsetX: 0
|
OffsetY: 0
|
OffsetY: 0
|
StateBar_End
|
StateBar_End
|
StateBar
|
StateBar
|
State_Name: C6
|
State_Name: C6
|
Line_Type: Dashed
|
Line_Type: Dashed
|
Edge_Position: 50
|
Edge_Position: 50
|
State_Color: #000000
|
State_Color: #000000
|
Font_Name: Dialog
|
Font_Name: Dialog
|
Font_Style: 0
|
Font_Style: 0
|
Font_Size: 12
|
Font_Size: 12
|
Signal_Type: DigitalClock
|
Signal_Type: DigitalClock
|
Signal_Name: aclk_i
|
Signal_Name: aclk_i
|
Edge_At: 13
|
Edge_At: 13
|
OffsetX: 0
|
OffsetX: 0
|
OffsetY: 0
|
OffsetY: 0
|
StateBar_End
|
StateBar_End
|
StateBar
|
StateBar
|
State_Name: C7
|
State_Name: C7
|
Line_Type: Dashed
|
Line_Type: Dashed
|
Edge_Position: 50
|
Edge_Position: 50
|
State_Color: #000000
|
State_Color: #000000
|
Font_Name: Dialog
|
Font_Name: Dialog
|
Font_Style: 0
|
Font_Style: 0
|
Font_Size: 12
|
Font_Size: 12
|
Signal_Type: DigitalClock
|
Signal_Type: DigitalClock
|
Signal_Name: aclk_i
|
Signal_Name: aclk_i
|
Edge_At: 15
|
Edge_At: 15
|
OffsetX: 0
|
OffsetX: 0
|
OffsetY: 0
|
OffsetY: 0
|
StateBar_End
|
StateBar_End
|
StateBar
|
StateBar
|
State_Name: C0
|
State_Name: C0
|
Line_Type: Dashed
|
Line_Type: Dashed
|
Edge_Position: 50
|
Edge_Position: 50
|
State_Color: #000000
|
State_Color: #000000
|
Font_Name: Dialog
|
Font_Name: Dialog
|
Font_Style: 0
|
Font_Style: 0
|
Font_Size: 12
|
Font_Size: 12
|
Signal_Type: DigitalClock
|
Signal_Type: DigitalClock
|
Signal_Name: aclk_i
|
Signal_Name: aclk_i
|
Edge_At: 1
|
Edge_At: 1
|
OffsetX: 0
|
OffsetX: 0
|
OffsetY: 0
|
OffsetY: 0
|
StateBar_End
|
StateBar_End
|
|
|
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