//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Low Pass Filter FIR IP Core ////
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//// Low Pass Filter FIR IP Core ////
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//// ////
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//// ////
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//// This file is part of the LPFFIR project ////
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//// This file is part of the LPFFIR project ////
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//// https://opencores.org/projects/lpffir ////
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//// https://opencores.org/projects/lpffir ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Implementation of LPFFIR IP core according to ////
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//// Implementation of LPFFIR IP core according to ////
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//// LPFFIR IP core specification document. ////
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//// LPFFIR IP core specification document. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - ////
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//// - ////
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//// ////
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//// ////
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//// Author: ////
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//// Author: ////
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//// - Vladimir Armstrong, vladimirarmstrong@opencores.org ////
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//// - Vladimir Armstrong, vladimirarmstrong@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module lpffir_core (
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module lpffir_core (
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input [15:0] x_i,
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input clk_i,
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input clk_i,
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input rstn_i,
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input en_i,
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input [15:0] x_i,
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output logic [15:0] y_o
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output logic [15:0] y_o
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);
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);
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reg [15:0] x1;
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reg [15:0] x1;
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reg [15:0] x2;
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reg [15:0] x2;
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reg [15:0] x3;
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reg [15:0] x3;
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reg [15:0] x4;
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reg [15:0] x4;
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reg [15:0] x5;
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reg [15:0] x5;
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logic [15:0] h0;
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logic [15:0] h0;
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logic [15:0] h1;
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logic [15:0] h1;
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logic [15:0] h2;
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logic [15:0] h2;
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logic [15:0] h01;
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logic [15:0] h01;
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logic co0;
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logic co0;
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logic co1;
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logic co1;
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logic co2;
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logic co2;
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logic co3;
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logic co3;
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logic co4;
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logic co4;
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// Linear-phase FIR structure
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// Linear-phase FIR structure
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rca rca_inst0 (.a(x_i),.b(x5),.ci(0),.co(co0),.s(h0));
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rca rca_inst0 (.a(x_i),.b(x5),.ci(0),.co(co0),.s(h0));
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rca rca_inst1 (.a(x1),.b(x4),.ci(0),.co(co1),.s(h1));
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rca rca_inst1 (.a(x1),.b(x4),.ci(0),.co(co1),.s(h1));
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rca rca_inst2 (.a(x2),.b(x3),.ci(0),.co(co2),.s(h2));
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rca rca_inst2 (.a(x2),.b(x3),.ci(0),.co(co2),.s(h2));
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rca rca_inst3 (.a(h0),.b(h1),.ci(0),.co(co3),.s(h01));
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rca rca_inst3 (.a(h0),.b(h1),.ci(0),.co(co3),.s(h01));
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rca rca_inst4 (.a(h01),.b(h2),.ci(0),.co(co4),.s(y_o));
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rca rca_inst4 (.a(h01),.b(h2),.ci(0),.co(co4),.s(y_o));
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always_ff @(posedge clk_i)
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always_ff @(posedge clk_i or posedge rstn_i)
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if(!rstn_i)
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begin
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x1 <= 0;
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x2 <= 0;
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x3 <= 0;
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x4 <= 0;
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x5 <= 0;
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end
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else if (en_i)
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begin
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begin
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x1 <= x_i;
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x1 <= x_i;
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x2 <= x1;
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x2 <= x1;
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x3 <= x2;
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x3 <= x2;
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x4 <= x3;
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x4 <= x3;
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x5 <= x4;
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x5 <= x4;
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end
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end
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endmodule
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endmodule
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