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[/] [lwrisc/] [trunk/] [RTL/] [memory.v] - Diff between revs 17 and 19
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Rev 19 |
/******************************************************************
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/******************************************************************
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* *
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* *
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* Author: Liwei *
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* Author: Liwei *
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* *
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* *
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* This file is part of the "ClaiRISC" project, *
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* This file is part of the "ClaiRISC" project, *
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* The folder in CVS is named as "lwrisc" *
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* The folder in CVS is named as "lwrisc" *
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* Downloaded from: *
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* Downloaded from: *
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* http://www.opencores.org/pdownloads.cgi/list/lwrisc *
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* http://www.opencores.org/pdownloads.cgi/list/lwrisc *
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* *
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* *
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* If you encountered any problem, please contact me via *
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* If you encountered any problem, please contact me via *
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* Email:mcupro@opencores.org or mcupro@163.com *
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* Email:mcupro@opencores.org or mcupro@163.com *
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* *
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* *
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******************************************************************/
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******************************************************************/
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`include "clairisc_def.h"
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`include "clairisc_def.h"
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`include "rom_set.h"
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`include "rom_set.h"
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module com_prom (
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module com_prom (
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clk,
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clk,
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rd_addr,
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rd_addr,
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dout
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dout
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);
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);
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input clk;
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input clk;
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input [10:0] rd_addr;
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input [10:0] rd_addr;
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output [11:0] dout;
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output [11:0] dout;
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`ifdef SIM
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`ifdef SIM
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sim_rom i_sim_ram(
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sim_rom i_sim_ram(
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.address(rd_addr),
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.address(rd_addr),
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.clock(clk),
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.clock(clk),
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.q(dout)
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.q(dout)
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);
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);
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`else
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`else
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`ROM_TYPE i_alt_ram (
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`ROM_TYPE i_alt_ram (
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.address(rd_addr),
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.address(rd_addr),
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.clock(clk),
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.clock(clk),
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.q(dout)
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.q(dout)
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);
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);
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`endif
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`endif
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endmodule
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endmodule
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module sim_reg_file (
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module sim_reg_file (
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data,
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data,
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wren,
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wren,
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wraddress,
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wraddress,
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rdaddress,
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rdaddress,
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clock,
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clock,
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q);
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q);
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input [7:0] data;
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input [7:0] data;
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input wren;
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input wren;
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input [6:0] wraddress;
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input [6:0] wraddress;
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input [6:0] rdaddress;
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input [6:0] rdaddress;
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input clock;
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input clock;
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output [7:0] q;
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output [7:0] q;
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reg [7:0] membank[0:127];
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reg [7:0] membank[0:127];
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reg r_we;
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reg r_we;
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reg [6:0] r_rd_addr;
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reg [6:0] r_rd_addr;
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reg [6:0] r_wr_addr;
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reg [6:0] r_wr_addr;
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reg [6:0] r_data;
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reg [6:0] r_data;
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always @ (posedge clock)
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always @ (posedge clock)
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begin
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begin
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r_rd_addr<=rdaddress;
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r_rd_addr<=rdaddress;
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r_wr_addr<=wraddress;
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r_wr_addr<=wraddress;
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r_data<=data;
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r_data<=data;
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r_we<=wren;
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r_we<=wren;
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end
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end
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always @(posedge clock)
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always @(posedge clock)
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if (r_we)
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if (r_we)
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membank[r_wr_addr]<=r_data;
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membank[r_wr_addr]<=r_data;
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assign q=((r_rd_addr==r_wr_addr)&&(r_we))?r_data:membank[r_rd_addr] ;
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assign q=((r_rd_addr==r_wr_addr)&&(r_we))?r_data:membank[r_rd_addr] ;
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endmodule
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endmodule
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