#-- Synplicity, Inc.
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#-- Synplicity, Inc.
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#-- Version Synplify Pro 8.1
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#-- Version Synplify Pro 8.1
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#-- Project file D:\LWRISC\SYN\ClaiRISC_core.prj
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#-- Project file D:\LWRISC\SYN\ClaiRISC_core.prj
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#-- Written on Mon Mar 10 17:43:02 2008
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#-- Written on Mon Mar 10 17:43:02 2008
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#add_file options
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#add_file options
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add_file -verilog "../RTL/sim_rom.v"
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add_file -verilog "../RTL/sim_rom.v"
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add_file -verilog "../RTL/test.v"
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add_file -verilog "../RTL/test.v"
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add_file -_include "../RTL/clairisc_def.h"
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add_file -_include "../RTL/clairisc_def.h"
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add_file -verilog "../RTL/mem_man.v"
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add_file -verilog "../RTL/mem_man.v"
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add_file -verilog "../RTL/memory.v"
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add_file -verilog "../RTL/memory.v"
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add_file -verilog "../RTL/risc_core.v"
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add_file -verilog "../RTL/risc_core.v"
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add_file -_include "../RTL/rom_set.h"
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add_file -_include "../RTL/rom_set.h"
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add_file -verilog "../RTL/altera/rom512x12.v"
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add_file -verilog "../RTL/altera/rom512x12.v"
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add_file -verilog "../RTL/altera/rom1024x12.v"
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add_file -verilog "../RTL/altera/rom1024x12.v"
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add_file -verilog "../RTL/altera/rom2048x12.v"
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add_file -verilog "../RTL/altera/rom2048x12.v"
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add_file -verilog "../RTL/altera/ram128x8.v"
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add_file -verilog "../RTL/altera/ram128x8.v"
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add_file -verilog "../RTL/altera/rom32x12.v"
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add_file -verilog "../RTL/altera/rom32x12.v"
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add_file -verilog "../RTL/altera/rom64x12.v"
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add_file -verilog "../RTL/altera/rom64x12.v"
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add_file -verilog "../RTL/altera/rom128x12.v"
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add_file -verilog "../RTL/altera/rom128x12.v"
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add_file -verilog "../RTL/altera/rom256x12.v"
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add_file -verilog "../RTL/altera/rom256x12.v"
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#implementation: "rev_1"
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#implementation: "rev_1"
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impl -add rev_1
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impl -add rev_1
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#device options
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#device options
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set_option -technology CYCLONE
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set_option -technology CYCLONE
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set_option -part EP1C6
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set_option -part EP1C6
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set_option -package QC240
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set_option -package QC240
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set_option -speed_grade -6
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set_option -speed_grade -6
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#compilation/mapping options
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#compilation/mapping options
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set_option -default_enum_encoding onehot
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set_option -default_enum_encoding onehot
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set_option -symbolic_fsm_compiler 1
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set_option -symbolic_fsm_compiler 1
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set_option -resource_sharing 1
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set_option -resource_sharing 1
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set_option -use_fsm_explorer 0
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set_option -use_fsm_explorer 0
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set_option -top_module "ClaiRISC_core"
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set_option -top_module "ClaiRISC_core"
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#map options
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#map options
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set_option -frequency auto
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set_option -frequency auto
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set_option -run_prop_extract 0
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set_option -run_prop_extract 0
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set_option -fanout_limit 30
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set_option -fanout_limit 30
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set_option -disable_io_insertion 0
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set_option -disable_io_insertion 0
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set_option -verification_mode 0
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set_option -verification_mode 0
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set_option -pipe 1
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set_option -pipe 1
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set_option -update_models_cp 0
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set_option -update_models_cp 0
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set_option -retiming 1
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set_option -retiming 1
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set_option -fixgatedclocks 0
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set_option -fixgatedclocks 0
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set_option -no_sequential_opt 0
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set_option -no_sequential_opt 0
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#simulation options
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#simulation options
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set_option -write_verilog 0
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set_option -write_verilog 0
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set_option -write_vhdl 0
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set_option -write_vhdl 0
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#VIF options
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#VIF options
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set_option -write_vif 1
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set_option -write_vif 1
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#automatic place and route (vendor) options
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 1
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set_option -write_apr_constraint 1
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#set result format/file last
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#set result format/file last
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project -result_file "rev_1/ClaiRISC_core.vqm"
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project -result_file "rev_1/ClaiRISC_core.vqm"
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#
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#
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#implementation attributes
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#implementation attributes
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set_option -vlog_std v2001
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set_option -vlog_std v2001
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set_option -dup 0
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set_option -dup 0
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set_option -project_relative_includes 1
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set_option -project_relative_includes 1
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#par_1 attributes
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#par_1 attributes
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set_option -job par_1 -add par
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set_option -job par_1 -add par
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set_option -job par_1 -option run_backannotation 0
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set_option -job par_1 -option run_backannotation 0
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impl -active "rev_1"
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impl -active "rev_1"
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