---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- Complementor
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-- Complementor
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--
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--
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-- Part of the LXP32 CPU
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-- Part of the LXP32 CPU
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- Computes a 2's complement of its input. Used as an auxiliary
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-- Computes a 2's complement of its input. Used as an auxiliary
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-- unit in the divider.
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-- unit in the divider.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity lxp32_compl is
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entity lxp32_compl is
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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compl_i: in std_logic;
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compl_i: in std_logic;
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d_i: in std_logic_vector(31 downto 0);
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d_i: in std_logic_vector(31 downto 0);
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d_o: out std_logic_vector(31 downto 0)
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d_o: out std_logic_vector(31 downto 0)
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);
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);
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end entity;
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end entity;
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architecture rtl of lxp32_compl is
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architecture rtl of lxp32_compl is
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signal d_prepared: unsigned(d_i'range);
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signal d_prepared: unsigned(d_i'range);
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signal sum_low: unsigned(16 downto 0);
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signal sum_low: unsigned(16 downto 0);
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signal d_high: unsigned(15 downto 0);
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signal d_high: unsigned(15 downto 0);
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signal sum_high: unsigned(15 downto 0);
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signal sum_high: unsigned(15 downto 0);
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begin
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begin
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d_prepared_gen: for i in d_prepared'range generate
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d_prepared_gen: for i in d_prepared'range generate
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d_prepared(i)<=d_i(i) xor compl_i;
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d_prepared(i)<=d_i(i) xor compl_i;
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end generate;
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end generate;
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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sum_low<=("0"&d_prepared(15 downto 0))+(to_unsigned(0,16)&compl_i);
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sum_low<=("0"&d_prepared(15 downto 0))+(to_unsigned(0,16)&compl_i);
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d_high<=d_prepared(31 downto 16);
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d_high<=d_prepared(31 downto 16);
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end if;
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end if;
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end process;
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end process;
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sum_high<=d_high+(to_unsigned(0,15)&sum_low(sum_low'high));
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sum_high<=d_high+(to_unsigned(0,15)&sum_low(sum_low'high));
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d_o<=std_logic_vector(sum_high&sum_low(15 downto 0));
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d_o<=std_logic_vector(sum_high&sum_low(15 downto 0));
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end architecture;
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end architecture;
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