---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- Divider
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-- Divider
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--
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--
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-- Part of the LXP32 CPU
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-- Part of the LXP32 CPU
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- Based on the NRD (Non Restoring Division) algorithm. Takes
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-- Based on the NRD (Non Restoring Division) algorithm. Takes
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-- 36 cycles to calculate quotient (37 for remainder).
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-- 36 cycles to calculate quotient (37 for remainder).
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity lxp32_divider is
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entity lxp32_divider is
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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ce_i: in std_logic;
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ce_i: in std_logic;
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op1_i: in std_logic_vector(31 downto 0);
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op1_i: in std_logic_vector(31 downto 0);
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op2_i: in std_logic_vector(31 downto 0);
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op2_i: in std_logic_vector(31 downto 0);
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signed_i: in std_logic;
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signed_i: in std_logic;
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rem_i: in std_logic;
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rem_i: in std_logic;
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ce_o: out std_logic;
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ce_o: out std_logic;
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result_o: out std_logic_vector(31 downto 0)
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result_o: out std_logic_vector(31 downto 0)
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);
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);
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end entity;
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end entity;
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architecture rtl of lxp32_divider is
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architecture rtl of lxp32_divider is
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-- Complementor signals
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-- Complementor signals
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signal compl_inv: std_logic;
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signal compl_inv: std_logic;
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signal compl_mux: std_logic_vector(31 downto 0);
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signal compl_mux: std_logic_vector(31 downto 0);
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signal compl_out: std_logic_vector(31 downto 0);
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signal compl_out: std_logic_vector(31 downto 0);
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signal inv_res: std_logic;
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signal inv_res: std_logic;
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-- Divider FSM signals
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-- Divider FSM signals
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signal fsm_ce: std_logic:='0';
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signal fsm_ce: std_logic:='0';
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signal dividend: unsigned(31 downto 0);
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signal dividend: unsigned(31 downto 0);
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signal divisor: unsigned(32 downto 0);
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signal divisor: unsigned(32 downto 0);
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signal want_remainder: std_logic;
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signal want_remainder: std_logic;
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signal partial_remainder: unsigned(32 downto 0);
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signal partial_remainder: unsigned(32 downto 0);
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signal addend: unsigned(32 downto 0);
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signal addend: unsigned(32 downto 0);
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signal sum: unsigned(32 downto 0);
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signal sum: unsigned(32 downto 0);
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signal sum_positive: std_logic;
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signal sum_positive: std_logic;
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signal sum_subtract: std_logic;
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signal sum_subtract: std_logic;
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signal cnt: integer range 0 to 34:=0;
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signal cnt: integer range 0 to 34:=0;
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signal ceo: std_logic:='0';
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signal ceo: std_logic:='0';
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-- Output restoration signals
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-- Output restoration signals
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signal remainder_corrector: unsigned(31 downto 0);
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signal remainder_corrector: unsigned(31 downto 0);
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signal remainder_corrector_1: std_logic;
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signal remainder_corrector_1: std_logic;
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signal remainder_pos: unsigned(31 downto 0);
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signal remainder_pos: unsigned(31 downto 0);
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signal result_pos: unsigned(31 downto 0);
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signal result_pos: unsigned(31 downto 0);
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begin
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begin
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compl_inv<=op1_i(31) and signed_i when ce_i='1' else inv_res;
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compl_inv<=op1_i(31) and signed_i when ce_i='1' else inv_res;
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compl_mux<=op1_i when ce_i='1' else std_logic_vector(result_pos);
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compl_mux<=op1_i when ce_i='1' else std_logic_vector(result_pos);
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compl_op1_inst: entity work.lxp32_compl(rtl)
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compl_op1_inst: entity work.lxp32_compl(rtl)
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port map(
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port map(
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clk_i=>clk_i,
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clk_i=>clk_i,
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compl_i=>compl_inv,
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compl_i=>compl_inv,
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d_i=>compl_mux,
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d_i=>compl_mux,
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d_o=>compl_out
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d_o=>compl_out
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);
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);
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if rst_i='1' then
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if rst_i='1' then
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fsm_ce<='0';
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fsm_ce<='0';
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want_remainder<='-';
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want_remainder<='-';
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inv_res<='-';
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inv_res<='-';
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else
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else
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fsm_ce<=ce_i;
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fsm_ce<=ce_i;
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if ce_i='1' then
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if ce_i='1' then
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want_remainder<=rem_i;
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want_remainder<=rem_i;
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if rem_i='1' then
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if rem_i='1' then
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inv_res<=op1_i(31) and signed_i;
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inv_res<=op1_i(31) and signed_i;
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else
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else
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inv_res<=(op1_i(31) xor op2_i(31)) and signed_i;
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inv_res<=(op1_i(31) xor op2_i(31)) and signed_i;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Main adder/subtractor
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-- Main adder/subtractor
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addend_gen: for i in addend'range generate
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addend_gen: for i in addend'range generate
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addend(i)<=divisor(i) xor sum_subtract;
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addend(i)<=divisor(i) xor sum_subtract;
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end generate;
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end generate;
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sum<=partial_remainder+addend+(to_unsigned(0,32)&sum_subtract);
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sum<=partial_remainder+addend+(to_unsigned(0,32)&sum_subtract);
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sum_positive<=not sum(32);
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sum_positive<=not sum(32);
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-- Divider state machine
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-- Divider state machine
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if rst_i='1' then
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if rst_i='1' then
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cnt<=0;
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cnt<=0;
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ceo<='0';
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ceo<='0';
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divisor<=(others=>'-');
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divisor<=(others=>'-');
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dividend<=(others=>'-');
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dividend<=(others=>'-');
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partial_remainder<=(others=>'-');
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partial_remainder<=(others=>'-');
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sum_subtract<='-';
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sum_subtract<='-';
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else
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else
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if cnt=1 then
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if cnt=1 then
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ceo<='1';
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ceo<='1';
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else
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else
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ceo<='0';
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ceo<='0';
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end if;
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end if;
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if ce_i='1' then
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if ce_i='1' then
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divisor(31 downto 0)<=unsigned(op2_i);
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divisor(31 downto 0)<=unsigned(op2_i);
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divisor(32)<=op2_i(31) and signed_i;
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divisor(32)<=op2_i(31) and signed_i;
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end if;
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end if;
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if fsm_ce='1' then
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if fsm_ce='1' then
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dividend<=unsigned(compl_out(30 downto 0)&"0");
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dividend<=unsigned(compl_out(30 downto 0)&"0");
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partial_remainder<=to_unsigned(0,32)&compl_out(31);
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partial_remainder<=to_unsigned(0,32)&compl_out(31);
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sum_subtract<=not divisor(32);
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sum_subtract<=not divisor(32);
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if want_remainder='1' then
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if want_remainder='1' then
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cnt<=34;
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cnt<=34;
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else
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else
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cnt<=33;
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cnt<=33;
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end if;
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end if;
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else
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else
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partial_remainder<=sum(31 downto 0)÷nd(31);
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partial_remainder<=sum(31 downto 0)÷nd(31);
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sum_subtract<=sum_positive xor divisor(32);
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sum_subtract<=sum_positive xor divisor(32);
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dividend<=dividend(30 downto 0)&sum_positive;
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dividend<=dividend(30 downto 0)&sum_positive;
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if cnt>0 then
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if cnt>0 then
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cnt<=cnt-1;
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cnt<=cnt-1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Output restoration circuit
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-- Output restoration circuit
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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for i in remainder_corrector'range loop
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for i in remainder_corrector'range loop
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remainder_corrector(i)<=(divisor(i) xor divisor(32)) and not sum_positive;
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remainder_corrector(i)<=(divisor(i) xor divisor(32)) and not sum_positive;
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end loop;
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end loop;
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remainder_corrector_1<=divisor(32) and not sum_positive;
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remainder_corrector_1<=divisor(32) and not sum_positive;
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remainder_pos<=partial_remainder(32 downto 1)+remainder_corrector+
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remainder_pos<=partial_remainder(32 downto 1)+remainder_corrector+
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(to_unsigned(0,31)&remainder_corrector_1);
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(to_unsigned(0,31)&remainder_corrector_1);
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end if;
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end if;
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end process;
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end process;
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result_pos<=remainder_pos when want_remainder='1' else dividend;
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result_pos<=remainder_pos when want_remainder='1' else dividend;
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result_o<=compl_out;
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result_o<=compl_out;
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ce_o<=ceo;
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ce_o<=ceo;
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end architecture;
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end architecture;
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