---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- Instruction fetch
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-- Instruction fetch
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--
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--
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-- Part of the LXP32 CPU
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-- Part of the LXP32 CPU
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- The first stage of the LXP32 pipeline.
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-- The first stage of the LXP32 pipeline.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity lxp32_fetch is
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entity lxp32_fetch is
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generic(
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generic(
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START_ADDR: std_logic_vector(29 downto 0)
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START_ADDR: std_logic_vector(31 downto 0)
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);
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);
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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lli_re_o: out std_logic;
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lli_re_o: out std_logic;
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lli_adr_o: out std_logic_vector(29 downto 0);
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lli_adr_o: out std_logic_vector(29 downto 0);
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lli_dat_i: in std_logic_vector(31 downto 0);
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lli_dat_i: in std_logic_vector(31 downto 0);
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lli_busy_i: in std_logic;
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lli_busy_i: in std_logic;
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word_o: out std_logic_vector(31 downto 0);
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word_o: out std_logic_vector(31 downto 0);
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current_ip_o: out std_logic_vector(29 downto 0);
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next_ip_o: out std_logic_vector(29 downto 0);
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next_ip_o: out std_logic_vector(29 downto 0);
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valid_o: out std_logic;
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valid_o: out std_logic;
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ready_i: in std_logic;
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ready_i: in std_logic;
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jump_valid_i: in std_logic;
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jump_valid_i: in std_logic;
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jump_dst_i: in std_logic_vector(29 downto 0);
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jump_dst_i: in std_logic_vector(29 downto 0);
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jump_ready_o: out std_logic
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jump_ready_o: out std_logic
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);
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);
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end entity;
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end entity;
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architecture rtl of lxp32_fetch is
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architecture rtl of lxp32_fetch is
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signal init: std_logic:='1';
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signal init: std_logic:='1';
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signal init_cnt: unsigned(7 downto 0):=(others=>'0');
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signal init_cnt: unsigned(7 downto 0):=(others=>'0');
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signal fetch_addr: std_logic_vector(29 downto 0):=START_ADDR;
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signal fetch_addr: std_logic_vector(29 downto 0):=START_ADDR(31 downto 2);
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signal next_word: std_logic;
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signal next_word: std_logic;
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signal suppress_re: std_logic:='0';
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signal suppress_re: std_logic:='0';
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signal re: std_logic;
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signal re: std_logic;
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signal requested: std_logic:='0';
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signal requested: std_logic:='0';
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signal fifo_rst: std_logic;
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signal fifo_rst: std_logic;
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signal fifo_we: std_logic;
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signal fifo_we: std_logic;
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signal fifo_din: std_logic_vector(61 downto 0);
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signal fifo_din: std_logic_vector(31 downto 0);
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signal fifo_re: std_logic;
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signal fifo_re: std_logic;
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signal fifo_dout: std_logic_vector(61 downto 0);
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signal fifo_dout: std_logic_vector(31 downto 0);
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signal fifo_empty: std_logic;
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signal fifo_empty: std_logic;
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signal fifo_full: std_logic;
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signal fifo_full: std_logic;
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signal jr: std_logic:='0';
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signal jr: std_logic:='0';
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signal next_ip: std_logic_vector(fetch_addr'range);
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signal current_ip: std_logic_vector(fetch_addr'range);
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begin
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begin
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-- INIT state machine (to initialize all registers)
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-- INIT state machine (to initialize all registers)
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-- All CPU registers are expected to be zero-initialized after reset.
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-- All CPU registers are expected to be zero-initialized after reset.
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-- Since these registers are implemented as a RAM block, we perform
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-- Since these registers are implemented as a RAM block, we perform
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-- the initialization sequentially by generating "mov rN, 0" instructions
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-- the initialization sequentially by generating "mov rN, 0" instructions
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-- for each N from 0 to 255.
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-- for each N from 0 to 255.
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--
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--
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-- With SRAM-based FPGAs, flip-flops and RAM blocks have deterministic
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-- With SRAM-based FPGAs, flip-flops and RAM blocks have deterministic
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-- state after configuration. On these technologies the CPU can operate
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-- state after configuration. On these technologies the CPU can operate
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-- without reset and the initialization procedure described above is not
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-- without reset and the initialization procedure described above is not
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-- needed. However, the initialization is still performed as usual when
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-- needed. However, the initialization is still performed as usual when
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-- external reset signal is asserted.
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-- external reset signal is asserted.
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if rst_i='1' then
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if rst_i='1' then
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init<='0';
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init<='0';
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init_cnt<=(others=>'0');
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init_cnt<=(others=>'0');
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else
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else
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if init='0' and ready_i='1' then
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if init='0' and ready_i='1' then
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init_cnt<=init_cnt+1;
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init_cnt<=init_cnt+1;
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if init_cnt=X"FF" then
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if init_cnt=X"FF" then
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init<='1';
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init<='1';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- FETCH state machine
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-- FETCH state machine
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if rst_i='1' then
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if rst_i='1' then
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fetch_addr<=START_ADDR;
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fetch_addr<=START_ADDR(31 downto 2);
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requested<='0';
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requested<='0';
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jr<='0';
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jr<='0';
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suppress_re<='0';
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suppress_re<='0';
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next_ip<=(others=>'-');
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else
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else
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jr<='0';
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jr<='0';
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-- Suppress LLI request if jump signal is active but will not be processed
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-- Suppress LLI request if jump signal is active but will not be processed
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-- in this cycle. Helps to reduce jump latency with high-latency LLI slaves.
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-- in this cycle. Helps to reduce jump latency with high-latency LLI slaves.
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-- Note: gating "re" with "jump_valid_i and not jr" asynchronously would
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-- Note: gating "re" with "jump_valid_i and not jr" asynchronously would
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-- reduce jump latency even more, but we really want to avoid too large
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-- reduce jump latency even more, but we really want to avoid too large
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-- clock-to-out on LLI outputs.
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-- clock-to-out on LLI outputs.
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suppress_re<=jump_valid_i and not jr and not next_word;
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suppress_re<=jump_valid_i and not jr and not next_word;
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if lli_busy_i='0' then
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if lli_busy_i='0' then
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requested<=re and not (jump_valid_i and not jr);
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requested<=re and not (jump_valid_i and not jr);
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end if;
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end if;
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if next_word='1' then
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if next_word='1' then
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-- It's not immediately obvious why, but current_ip and next_ip will contain
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-- the addresses of the current instruction and the next instruction to be
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-- fetched, respectively, by the time the instruction is passed to the decode
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-- stage. Basically, this is because when either the decoder or the IBUS
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-- stalls, the fetch_addr counter will also stop incrementing.
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next_ip<=fetch_addr;
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current_ip<=next_ip;
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if jump_valid_i='1' and jr='0' then
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if jump_valid_i='1' and jr='0' then
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fetch_addr<=jump_dst_i;
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fetch_addr<=jump_dst_i;
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jr<='1';
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jr<='1';
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else
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else
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fetch_addr<=std_logic_vector(unsigned(fetch_addr)+1);
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fetch_addr<=std_logic_vector(unsigned(fetch_addr)+1);
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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next_word<=(fifo_empty or ready_i) and not lli_busy_i and init;
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next_word<=(fifo_empty or ready_i) and not lli_busy_i and init;
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re<=(fifo_empty or ready_i) and init and not suppress_re;
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re<=(fifo_empty or ready_i) and init and not suppress_re;
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lli_re_o<=re;
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lli_re_o<=re;
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lli_adr_o<=fetch_addr;
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lli_adr_o<=fetch_addr;
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jump_ready_o<=jr;
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jump_ready_o<=jr;
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-- Small instruction buffer
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-- Small instruction buffer
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fifo_rst<=rst_i or (jump_valid_i and not jr);
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fifo_rst<=rst_i or (jump_valid_i and not jr);
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fifo_we<=requested and not lli_busy_i;
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fifo_we<=requested and not lli_busy_i;
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fifo_din<=fetch_addr&lli_dat_i;
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fifo_din<=lli_dat_i;
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fifo_re<=ready_i and not fifo_empty;
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fifo_re<=ready_i and not fifo_empty;
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ubuf_inst: entity work.lxp32_ubuf(rtl)
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ubuf_inst: entity work.lxp32_ubuf(rtl)
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generic map(
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generic map(
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DATA_WIDTH=>62
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DATA_WIDTH=>32
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)
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)
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port map(
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port map(
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clk_i=>clk_i,
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clk_i=>clk_i,
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rst_i=>fifo_rst,
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rst_i=>fifo_rst,
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we_i=>fifo_we,
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we_i=>fifo_we,
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d_i=>fifo_din,
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d_i=>fifo_din,
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re_i=>fifo_re,
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re_i=>fifo_re,
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d_o=>fifo_dout,
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d_o=>fifo_dout,
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empty_o=>fifo_empty,
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empty_o=>fifo_empty,
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full_o=>fifo_full
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full_o=>fifo_full
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);
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);
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next_ip_o<=fifo_dout(61 downto 32);
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next_ip_o<=next_ip;
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current_ip_o<=current_ip;
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word_o<=fifo_dout(31 downto 0) when init='1' else X"40"&std_logic_vector(init_cnt)&X"0000";
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word_o<=fifo_dout when init='1' else X"40"&std_logic_vector(init_cnt)&X"0000";
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valid_o<=not fifo_empty or not init;
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valid_o<=not fifo_empty or not init;
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-- Note: the following code contains a few simulation-only assertions
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-- to check that current_ip and next_ip signals, used in procedure calls
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-- and interrupts, are correct.
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-- This code should be ignored by a synthesizer since it doesn't drive
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-- any signals, but we also surround it by metacomments, just in case.
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-- synthesis translate_off
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process (clk_i) is
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type Pair is record
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addr: std_logic_vector(fetch_addr'range);
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data: std_logic_vector(31 downto 0);
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end record;
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type Pairs is array (7 downto 0) of Pair;
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variable buf: Pairs;
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variable count: integer range buf'range:=0;
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variable current_pair: Pair;
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begin
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if rising_edge(clk_i) then
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if fifo_rst='1' then -- jump
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count:=0;
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elsif fifo_we='1' then -- LLI returned data
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current_pair.data:=fifo_din;
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buf(count):=current_pair;
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count:=count+1;
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end if;
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if re='1' and lli_busy_i='0' then -- data requested
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current_pair.addr:=fetch_addr;
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end if;
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if fifo_empty='0' and fifo_rst='0' then -- fetch output is valid
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assert count>0
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report "Fetch: buffer should be empty"
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severity failure;
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assert buf(0).data=fifo_dout
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report "Fetch: incorrect data"
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severity failure;
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assert buf(0).addr=current_ip
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report "Fetch: incorrect current_ip"
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severity failure;
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assert std_logic_vector(unsigned(buf(0).addr)+1)=next_ip
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report "Fetch: incorrect next_ip"
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severity failure;
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if ready_i='1' then
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buf(buf'high-1 downto 0):=buf(buf'high downto 1); -- we don't care about the highest item
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count:=count-1;
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end if;
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end if;
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end if;
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end process;
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-- synthesis translate_on
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end architecture;
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end architecture;
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