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[/] [lxp32/] [trunk/] [rtl/] [lxp32_mul16x16.vhd] - Diff between revs 2 and 9
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- A basic parallel 16x16 multiplier with an output register
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-- A basic parallel 16x16 multiplier with an output register
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--
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--
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-- Part of the LXP32 CPU
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-- Part of the LXP32 CPU
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- A straightforward behavioral description. Can be replaced
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-- A straightforward behavioral description. Can be replaced
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-- with a library component wrapper if needed.
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-- with a library component wrapper if needed.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity lxp32_mul16x16 is
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entity lxp32_mul16x16 is
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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a_i: in std_logic_vector(15 downto 0);
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a_i: in std_logic_vector(15 downto 0);
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b_i: in std_logic_vector(15 downto 0);
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b_i: in std_logic_vector(15 downto 0);
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p_o: out std_logic_vector(31 downto 0)
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p_o: out std_logic_vector(31 downto 0)
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);
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);
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end entity;
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end entity;
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architecture rtl of lxp32_mul16x16 is
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architecture rtl of lxp32_mul16x16 is
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begin
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begin
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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p_o<=std_logic_vector(unsigned(a_i)*unsigned(b_i));
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p_o<=std_logic_vector(unsigned(a_i)*unsigned(b_i));
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end if;
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end if;
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end process;
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end process;
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end architecture;
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end architecture;
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