---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- Optimized multiplier
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-- Optimized multiplier
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--
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--
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-- Part of the LXP32 CPU
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-- Part of the LXP32 CPU
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- This multiplier is designed for technologies that don't provide
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-- This multiplier is designed for technologies that don't provide
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-- fast 16x16 multipliers. One multiplication takes 6 cycles.
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-- fast 16x16 multipliers. One multiplication takes 6 cycles.
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--
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--
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-- The multiplication algorithm is based on carry-save accumulation
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-- The multiplication algorithm is based on carry-save accumulation
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-- of partial products.
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-- of partial products.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity lxp32_mul_opt is
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entity lxp32_mul_opt is
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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ce_i: in std_logic;
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ce_i: in std_logic;
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op1_i: in std_logic_vector(31 downto 0);
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op1_i: in std_logic_vector(31 downto 0);
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op2_i: in std_logic_vector(31 downto 0);
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op2_i: in std_logic_vector(31 downto 0);
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ce_o: out std_logic;
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ce_o: out std_logic;
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result_o: out std_logic_vector(31 downto 0)
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result_o: out std_logic_vector(31 downto 0)
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);
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);
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end entity;
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end entity;
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architecture rtl of lxp32_mul_opt is
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architecture rtl of lxp32_mul_opt is
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function csa_sum(a: unsigned; b: unsigned; c: unsigned; n: integer) return unsigned is
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function csa_sum(a: unsigned; b: unsigned; c: unsigned; n: integer) return unsigned is
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variable r: unsigned(n-1 downto 0);
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variable r: unsigned(n-1 downto 0);
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begin
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begin
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for i in r'range loop
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for i in r'range loop
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r(i):=a(i) xor b(i) xor c(i);
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r(i):=a(i) xor b(i) xor c(i);
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end loop;
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end loop;
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return r;
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return r;
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end function;
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end function;
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function csa_carry(a: unsigned; b: unsigned; c: unsigned; n: integer) return unsigned is
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function csa_carry(a: unsigned; b: unsigned; c: unsigned; n: integer) return unsigned is
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variable r: unsigned(n-1 downto 0);
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variable r: unsigned(n-1 downto 0);
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begin
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begin
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for i in r'range loop
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for i in r'range loop
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r(i):=(a(i) and b(i)) or (a(i) and c(i)) or (b(i) and c(i));
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r(i):=(a(i) and b(i)) or (a(i) and c(i)) or (b(i) and c(i));
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end loop;
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end loop;
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return r&"0";
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return r&"0";
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end function;
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end function;
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signal reg1: unsigned(op1_i'range);
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signal reg1: unsigned(op1_i'range);
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signal reg2: unsigned(op2_i'range);
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signal reg2: unsigned(op2_i'range);
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type pp_type is array (7 downto 0) of unsigned(31 downto 0);
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type pp_type is array (7 downto 0) of unsigned(31 downto 0);
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signal pp: pp_type;
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signal pp: pp_type;
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type pp_sum_type is array (7 downto 0) of unsigned(31 downto 0);
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type pp_sum_type is array (7 downto 0) of unsigned(31 downto 0);
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signal pp_sum: pp_sum_type;
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signal pp_sum: pp_sum_type;
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type pp_carry_type is array (7 downto 0) of unsigned(32 downto 0);
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type pp_carry_type is array (7 downto 0) of unsigned(32 downto 0);
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signal pp_carry: pp_carry_type;
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signal pp_carry: pp_carry_type;
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signal acc_sum: unsigned(31 downto 0);
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signal acc_sum: unsigned(31 downto 0);
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signal acc_carry: unsigned(31 downto 0);
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signal acc_carry: unsigned(31 downto 0);
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signal cnt: integer range 0 to 4:=0;
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signal cnt: integer range 0 to 4:=0;
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signal result: std_logic_vector(result_o'range);
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signal result: std_logic_vector(result_o'range);
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signal ceo: std_logic:='0';
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signal ceo: std_logic:='0';
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begin
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begin
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-- Calculate 8 partial products in parallel
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-- Calculate 8 partial products in parallel
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pp_gen: for i in pp'range generate
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pp_gen: for i in pp'range generate
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pp(i)<=shift_left(reg1,i) when reg2(i)='1' else (others=>'0');
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pp(i)<=shift_left(reg1,i) when reg2(i)='1' else (others=>'0');
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end generate;
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end generate;
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-- Add partial products to the accumulator using carry-save adder tree
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-- Add partial products to the accumulator using carry-save adder tree
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pp_sum(0)<=csa_sum(pp(0),pp(1),pp(2),32);
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pp_sum(0)<=csa_sum(pp(0),pp(1),pp(2),32);
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pp_carry(0)<=csa_carry(pp(0),pp(1),pp(2),32);
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pp_carry(0)<=csa_carry(pp(0),pp(1),pp(2),32);
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pp_sum(1)<=csa_sum(pp(3),pp(4),pp(5),32);
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pp_sum(1)<=csa_sum(pp(3),pp(4),pp(5),32);
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pp_carry(1)<=csa_carry(pp(3),pp(4),pp(5),32);
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pp_carry(1)<=csa_carry(pp(3),pp(4),pp(5),32);
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pp_sum(2)<=csa_sum(pp(6),pp(7),acc_sum,32);
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pp_sum(2)<=csa_sum(pp(6),pp(7),acc_sum,32);
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pp_carry(2)<=csa_carry(pp(6),pp(7),acc_sum,32);
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pp_carry(2)<=csa_carry(pp(6),pp(7),acc_sum,32);
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pp_sum(3)<=csa_sum(pp_sum(0),pp_carry(0),pp_sum(1),32);
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pp_sum(3)<=csa_sum(pp_sum(0),pp_carry(0),pp_sum(1),32);
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pp_carry(3)<=csa_carry(pp_sum(0),pp_carry(0),pp_sum(1),32);
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pp_carry(3)<=csa_carry(pp_sum(0),pp_carry(0),pp_sum(1),32);
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pp_sum(4)<=csa_sum(pp_carry(1),pp_sum(2),pp_carry(2),32);
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pp_sum(4)<=csa_sum(pp_carry(1),pp_sum(2),pp_carry(2),32);
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pp_carry(4)<=csa_carry(pp_carry(1),pp_sum(2),pp_carry(2),32);
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pp_carry(4)<=csa_carry(pp_carry(1),pp_sum(2),pp_carry(2),32);
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pp_sum(5)<=csa_sum(pp_sum(3),pp_carry(3),pp_sum(4),32);
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pp_sum(5)<=csa_sum(pp_sum(3),pp_carry(3),pp_sum(4),32);
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pp_carry(5)<=csa_carry(pp_sum(3),pp_carry(3),pp_sum(4),32);
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pp_carry(5)<=csa_carry(pp_sum(3),pp_carry(3),pp_sum(4),32);
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pp_sum(6)<=csa_sum(pp_sum(5),pp_carry(5),pp_carry(4),32);
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pp_sum(6)<=csa_sum(pp_sum(5),pp_carry(5),pp_carry(4),32);
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pp_carry(6)<=csa_carry(pp_sum(5),pp_carry(5),pp_carry(4),32);
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pp_carry(6)<=csa_carry(pp_sum(5),pp_carry(5),pp_carry(4),32);
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pp_sum(7)<=csa_sum(pp_sum(6),pp_carry(6),acc_carry,32);
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pp_sum(7)<=csa_sum(pp_sum(6),pp_carry(6),acc_carry,32);
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pp_carry(7)<=csa_carry(pp_sum(6),pp_carry(6),acc_carry,32);
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pp_carry(7)<=csa_carry(pp_sum(6),pp_carry(6),acc_carry,32);
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-- Multiplier state machine
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-- Multiplier state machine
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if rst_i='1' then
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if rst_i='1' then
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ceo<='0';
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ceo<='0';
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cnt<=0;
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cnt<=0;
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reg1<=(others=>'-');
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reg1<=(others=>'-');
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reg2<=(others=>'-');
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reg2<=(others=>'-');
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acc_sum<=(others=>'-');
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acc_sum<=(others=>'-');
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acc_carry<=(others=>'-');
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acc_carry<=(others=>'-');
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else
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else
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if cnt=1 then
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if cnt=1 then
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ceo<='1';
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ceo<='1';
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else
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else
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ceo<='0';
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ceo<='0';
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end if;
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end if;
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if ce_i='1' then
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if ce_i='1' then
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cnt<=4;
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cnt<=4;
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reg1<=unsigned(op1_i);
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reg1<=unsigned(op1_i);
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reg2<=unsigned(op2_i);
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reg2<=unsigned(op2_i);
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acc_sum<=(others=>'0');
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acc_sum<=(others=>'0');
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acc_carry<=(others=>'0');
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acc_carry<=(others=>'0');
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else
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else
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acc_sum<=pp_sum(7);
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acc_sum<=pp_sum(7);
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acc_carry<=pp_carry(7)(acc_carry'range);
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acc_carry<=pp_carry(7)(acc_carry'range);
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reg1<=reg1(reg1'high-8 downto 0)&X"00";
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reg1<=reg1(reg1'high-8 downto 0)&X"00";
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reg2<=X"00"®2(reg2'high downto 8);
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reg2<=X"00"®2(reg2'high downto 8);
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if cnt>0 then
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if cnt>0 then
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cnt<=cnt-1;
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cnt<=cnt-1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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result<=std_logic_vector(acc_sum+acc_carry);
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result<=std_logic_vector(acc_sum+acc_carry);
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result_o<=result;
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result_o<=result;
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ce_o<=ceo;
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ce_o<=ceo;
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-- A simulation-time multiplication check
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-- A simulation-time multiplication check
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-- synthesis translate_off
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-- synthesis translate_off
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process (clk_i) is
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process (clk_i) is
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variable p: unsigned(op1_i'length+op2_i'length-1 downto 0);
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variable p: unsigned(op1_i'length+op2_i'length-1 downto 0);
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if ce_i='1' then
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if ce_i='1' then
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p:=unsigned(op1_i)*unsigned(op2_i);
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p:=unsigned(op1_i)*unsigned(op2_i);
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elsif ceo='1' then
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elsif ceo='1' then
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assert result=std_logic_vector(p(result'range))
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assert result=std_logic_vector(p(result'range))
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report "Incorrect multiplication result"
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report "Incorrect multiplication result"
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severity failure;
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severity failure;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- synthesis translate_on
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-- synthesis translate_on
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end architecture;
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end architecture;
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